[특허]Integrated circuit package system including zero fillet resin

[미국특허] Integrated circuit package system including zero fillet resin 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/52 H01L-023/48 H01L-029/40
출원번호	UP-0307482 (2006-02-09)
등록번호	US-7750482 (2010-07-26)
발명자 / 주소	Pendse, Rajendra D.
출원인 / 주소	Stats Chippac Ltd.
대리인 / 주소	Ishimaru, Mikio
인용정보	피인용 횟수 : 3 인용 특허 : 218

초록 ▼

An integrated circuit packaging system comprised by providing a substrate with a first surface including conductive regions for receiving a flip chip die and a second surface including electrical contacts for external electrical connections. Providing the flip chip die over the substrate. Depositing a controlled volume of resin between the first surface of the substrate and the flip chip die and adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin.

대표청구항 ▼

What is claimed is: 1. A method of manufacturing an integrated circuit package comprising: providing a substrate with a first surface including conductive regions for receiving a flip chip die and a second surface including electrical contacts for external electrical connections; providing the flip chip die over the substrate; depositing a controlled volume of resin between the first surface of the substrate and the flip chip die including applying the resin in a volume insufficient to fill the volume of space between the first surface of the substrate and the flip chip die; and adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin contacting an interconnect between the flip chip die and the substrate. 2. The method of claim 1 wherein: providing the flip chip die includes a die selected from digital signal processor die, application specific integrated circuit die, or micro-processor die. 3. The method of claim 1 wherein: depositing the controlled volume of resin includes depositing a volume of resin sufficient for assuring adhesion and preventing fillet formation. 4. The method of claim 1 further comprising: providing a wire bond die over the flip chip die. 5. The method of claim 1 wherein: manufacturing the integrated circuit package includes forming package-on-package systems or package-in-package systems. 6. A method of manufacturing an integrated circuit package comprising: providing a substrate with a bond finger on a first surface and solder ball connections on a second surface; providing a flip chip die; depositing a controlled volume of resin between the first surface of the substrate and the flip chip die including applying the resin in a volume insufficient to fill the volume of space between the first surface of the substrate and the flip chip die; adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin; routing a zero fillet wire bond connection to connect to the medial bond finger region closest to the flip chip die; and depositing a molding compound. 7. The method of claim 6 wherein: providing the substrate includes a substrate selected from printed circuit boards, package substrates, silicon substrates or integrated circuit die. 8. The method of claim 6 wherein: forming the zero fillet resin includes a perimeter region void of resin or filled by a molding compound between the substrate and the flip chip die of about 3 mm in width. 9. The method of claim 6 wherein: depositing a controlled volume of resin includes pre-applying the resin to the flip chip die or to the substrate. 10. The method of claim 6 wherein: manufacturing the integrated circuit package includes forming package-on-package systems or package-in-package systems. 11. An integrated circuit packaging system comprising: a flip chip die; a substrate with a first surface including conductive regions for receiving the flip chip die and a second surface including electrical contacts for external electrical connections; and a controlled volume of resin between the first surface of the substrate and the flip chip die, wherein the controlled volume of resin does not extend to the perimeter of the flip chip die, produces a zero fillet resin contacting an interconnect between the flip chip die and the substrate. 12. The system as claimed in claim 11 wherein: the flip chip die includes a die selected from digital signal processor die, application specific integrated circuit die, or micro-processor die. 13. The system as claimed in claim 11 wherein: the controlled volume of resin includes a volume of resin sufficient for assuring adhesion and preventing fillet formation. 14. The system as claimed in claim 11 further comprising: a wire bond die over the flip chip die. 15. The system as claimed in claim 11 wherein: the integrated circuit packaging system includes package-on-package systems or package-in-package systems. 16. The system as claimed in claim 11 wherein: the substrate includes a bond finger on the first surface and solder ball connections on the second surface; a zero fillet wire bond connection connected to a medial bond finger region closest to the flip chip die; and a molding compound that encapsulates the packaging system. 17. The system as claimed in claim 16 wherein: the substrate includes the substrate selected from printed circuit boards, package substrates, silicon substrates or integrated circuit die. 18. The system as claimed in claim 16 wherein: the zero fillet resin includes a perimeter region void of resin or filled with a molding compound between the substrate and the flip chip die in the range of 1 to 3 mm in width. 19. The system as claimed in claim 16 wherein: the controlled volume of resin is applied primarily to the flip chip die or to the substrate. 20. The system as claimed in claim 16 wherein: the integrated circuit package includes package-on-package systems or package-in-package systems.

이 특허에 인용된 특허 (218) 인용/피인용 타임라인 분석

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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[미국특허] Integrated circuit package system including zero fillet resin 원문보기

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[미국특허] Integrated circuit package system including zero fillet resin 원문보기

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