IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
UP-0972583
(2008-01-10)
|
| 등록번호 |
US-7755165
(2010-08-02)
|
|
발명자
/ 주소 |
- Palanduz, Cengiz A.
- Wood, Dustin P.
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
Blakely, Sokoloff, Taylor & Zafman LLP
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| 인용정보 |
피인용 횟수 :
1 인용 특허 :
62 |
초록
▼
A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined location
A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.
대표청구항
▼
What is claimed is: 1. An apparatus comprising: a first capacitor structure comprising an integrated capacitor having a first ceramic material disposed between two electrodes; and a second capacitor structure comprising an integrated capacitor having a second ceramic material disposed between two e
What is claimed is: 1. An apparatus comprising: a first capacitor structure comprising an integrated capacitor having a first ceramic material disposed between two electrodes; and a second capacitor structure comprising an integrated capacitor having a second ceramic material disposed between two electrodes, wherein the first ceramic material and the second ceramic material have different operating temperature ratings, and wherein the first capacitor and the second capacitor are integrated into an insulative core substrate, wherein an operating temperature rating of the first ceramic material is greater than an operating temperature rating of the second ceramic material, wherein the core substrate has a substantially planar surface, and wherein the first capacitor structure and the second capacitor structure are attached to the substantially planar surface of the core substrate, wherein the substantially planar surface is an exposed surface, and wherein an entire of the first capacitor structure is positioned in an area under a die shadow. 2. The apparatus of claim 1, wherein the first capacitor structure is positioned in an area under a die shadow of a die side of the planar surface and the second capacitor is positioned in an area outside the die shadow. 3. The apparatus of claim 2, further comprising a microprocessor configured to heat an area under a die shadow of a die side of the substrate with a higher temperature than an area outside the die shadow of the die side, wherein the first ceramic material has a lower dielectric constant, k, than the second ceramic material, and wherein the first capacitor structure is positioned in locations heated with a higher temperature than locations where the second capacitor structure is placed. 4. The apparatus of claim 3, wherein the first ceramic material has a lower capacitance than the second ceramic material. 5. The apparatus of claim 2, wherein the first capacitor structure is positioned into the core substrate for first droop capacitance and the second capacitor structure is positioned for second droop capacitance. 6. The apparatus of claim 2, wherein an operating temperature rating of the first ceramic material is greater than an operating temperature rating of the second ceramic material and wherein the first capacitor structure is disposed within an area surrounded by the second capacitor structure. 7. The apparatus of claim 6, wherein the first capacitor structure is disposed within an area surrounded by a plurality of the second capacitor structures. 8. A system comprising: a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the microprocessor configured to heat an area under a die shadow of a die side of the substrate with a higher temperature than an area outside the die shadow of the die side, the substrate comprising a first capacitor structure attached to a planar surface of the substrate, the first capacitor comprising a first ceramic material disposed between two electrodes and a second capacitor structure comprising a second ceramic material disposed between two electrodes, wherein the first ceramic material and the second ceramic material have different operating temperature ratings, wherein an operating temperature rating of the first ceramic material is greater than an operating temperature rating of the second ceramic material, the area under the die shadow of the substrate includes the first capacitor structure, and the area outside the die shadow includes the second capacitor structure attached to the planar surface wherein the substantially planar surface is an exposed surface, and wherein the area under the die shadow includes an entire of the first capacitor structure. 9. The system of claim 8, wherein the first capacitor structure is coupled to a substantially planar surface of the substrate and the second capacitor structure is coupled to the same substantially planar surface of the substrate. 10. The system of claim 8, wherein the first capacitor structure is positioned on the substrate for first droop capacitance and the second capacitor structure is positioned for second droop capacitance. 11. The system of claim 10, wherein the first ceramic material has a lower capacitance than the second ceramic material, and wherein the first capacitor structure is disposed within an area surrounded by the second capacitor structure. 12. The system of claim 11, wherein the first capacitor structure is disposed within an area surrounded by a plurality of the second capacitor structures. 13. The system of claim 8, wherein an operating temperature rating of the first ceramic material is greater than an operating temperature rating of the second ceramic material and wherein the first capacitor structure is disposed within an area defined by the second capacitor structure. 14. The apparatus of claim 8, wherein the substrate comprises an insulative package substrate disposed between the microprocessor and the printed circuit board. 15. An apparatus comprising: a microprocessor configured to heat an hotter area under a die shadow of a die side of the substrate with a higher temperature than a cooler area beyond the die shadow of the substrate; a first capacitor structure comprising a first plurality of integrated capacitors formed from a same first ceramic material disposed between a first two electrodes and formed on and attached to a first generally planar shaped surface of an insulative core substrate; and a second capacitor structure comprising a second plurality of integrated capacitors formed from a same second ceramic material disposed between a second two electrodes and formed on and attached to the first generally planar shaped surface of the insulative core substrate, wherein the first ceramic material and the second ceramic material have different operating temperature ratings, wherein an operating temperature rating of the first ceramic material is selected to be greater than an operating temperature rating of the second ceramic material and the first capacitor structure is selected to be positioned in the hotter area, and the second capacitor structure is placed in the cooler area, and wherein the first generally planar shaped surface is an exposed surface. 16. The apparatus of claim 15, wherein the first capacitor structure is disposed within an area surround by the second capacitor structure. 17. The apparatus of claim 16, wherein the first capacitor structure is disposed within an area surrounded by a plurality of the second capacitor structures. 18. The apparatus of claim 15, wherein the core substrate is an insulative core substrate comprising one of an epoxy material, an organic substrate material, a fiberglass reinforced material, and a pre-preg material. 19. The apparatus of claim 15, wherein the core substrate comprises an insulative material, the first capacitor structure is oriented parallel to the second capacitor structure, the core substrate comprises a package substrate; and further comprising conductive vias formed through the first capacitor structure, the second capacitor structure and the core substrate.
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