[특허]Shielded structures to protect semiconductor devices

[미국특허] Shielded structures to protect semiconductor devices 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/28 H01L-023/02 G21F-003/00
출원번호	UP-0206435 (2005-08-17)
등록번호	US-7759774 (2010-08-09)
발명자 / 주소	Fraser, David Doyle, Brian
출원인 / 주소	Intel Corporation
대리인 / 주소	Blakely, Sokoloff, Taylor & Zafman LLP
인용정보	피인용 횟수 : 8 인용 특허 : 17

초록 ▼

An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

대표청구항 ▼

We claim: 1. An apparatus comprising: a semiconductor device integrally formed within a monocrystalline silicon substrate such that the semiconductor device is a part of the monocrystalline substrate; a Faraday cage that encloses said semiconductor device within a structure of metal that has an at least one vertical metal wall, wherein a bottom surface of said Faraday cage is formed on a top surface of said monocrystalline silicon substrate, and said bottom surface of said Faraday cage is below a top surface of said semiconductor device; and a patterned insulating layer within the Faraday cage and over the at least one semiconductor device; and an interconnect within the Faraday cage and over a top surface of the patterned insulating layer. 2. The apparatus of claim 1, further comprising a second semiconductor device located outside and adjacent to the Faraday cage. 3. The apparatus of claim 1, wherein the at least one vertical metal wall is made from one or more metal layers. 4. The apparatus of claim 1, wherein the interconnect is connected with the at least one semiconductor device and includes input/output leads that pass through the at least one vertical metal wall of the Faraday cage at one or more insulated locations. 5. The apparatus of claim 4, wherein the one or more insulated locations are made from one or more insulating layers. 6. The apparatus of claim 4, wherein the interconnect is constructed with a metal layer that is used to construct the Faraday cage. 7. The apparatus of claim 4, wherein the interconnect is located within the Faraday cage. 8. The apparatus of claim 4, wherein the interconnect is further located outside the Faraday cage. 9. The apparatus of claim 1, further comprising a filled via constructed with a metal layer used to construct the Faraday cage. 10. The apparatus of claim 9, wherein the filled via is located within the Faraday cage. 11. The apparatus on a substrate of claim 9, wherein the filled via is located outside the Faraday cage. 12. The apparatus on a substrate of claim 1, wherein the at least one semiconductor device can be chosen from the group consisting of MOS, CMOS, NMOS, PMOS, Bi-CMOS and DMOS. 13. An apparatus comprising: an at least one semiconductor device integrally formed within a monocrystalline silicon substrate such that the semiconductor device is a part of the monocrystalline substrate; an at least one patterned insulating layer including a filled via opening positioned over the at least one semiconductor device; an at least one metal layer positioned over the at least one insulating layer such that the at least one metal layer forms a first metal cage that encloses the at least one semiconductor device and has at least one vertical metal wall, wherein a bottom surface of said first metal cage is on a top surface of said monocrystalline silicon substrate, and said bottom surface of said first metal cage is below a top surface of said semiconductor device. 14. The apparatus of claim 13, further comprising a second semiconductor device positioned outside and adjacent the first metal cage. 15. The apparatus of claim 13, further comprising: a second metal cage that encloses a first interconnect and is positioned higher than the first metal cage; a second interconnect positioned outside the second metal cage; an at least one set of input/output leads that connect the first interconnect within the second metal cage to the second interconnect positioned outside the second metal cage. 16. An apparatus comprising: a semiconductor device integrally formed within a semiconductor substrate such that the semiconductor device is a part of the semiconductor substrate; and a Faraday cage that encloses said semiconductor device within a structure of metal, wherein a bottom surface of said Faraday cage is formed on a top surface of said semiconductor substrate, and said bottom surface of said Faraday cage is below a top surface of said semiconductor device. 17. The apparatus of claim 16, further comprising a patterned insulating layer within the Faraday cage and over the at least one semiconductor device. 18. The apparatus of claim 17, further comprising an interconnect within the Faraday cage and over a top surface of the patterned insulating layer. 19. The apparatus of claim 18, wherein said bottom surface of said Faraday cage is below a top surface of said semiconductor device. 20. The apparatus of claim 18, wherein said bottom surface is in direct contact with said top surface of said semiconductor substrate.

이 특허에 인용된 특허 (17) 인용/피인용 타임라인 분석

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Muyshondt Jorge E. (Austin TX) Parker Gary A. (Round Rock TX) Wilkie Bruce J. (Georgetown TX), Faraday cage for a printed circuit card.
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Ozmat Burhan (Dallas TX), Heat transfer module for ultra high density and silicon on silicon packaging applications.
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Fillion Raymond A. (Niskayuna NY) Kornrumpf William P. (Albany NY) Bernard Edward S. (Manlius NY), Hermetically packaged HDI electronic system.
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Kevin Kwong-Tai Chung, High-density electronic package, and method for making same.
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Castagnetti Ruggero ; Liu Yauh-Ching ; Ramesh Subramanian, Integrated circuit having embedded memory with electromagnetic shield.
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King David Robert ; Reis Bradley E. ; Rowan Joseph C., Lid assembly for shielding electronic components from EMI/RFI interferences.
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Carlson, Richard O.; Glascock, II, Homer H.; Loughran, James A.; Webster, Harold F., Low loss, multilevel silicon circuit board.
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Fraser, David; Doyle, Brian, Method of creating shielded structures to protect semiconductor devices.
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Tilmans Hendrikus A. C.,NLX ; Beyne Eric,BEX ; Van de Peer Myriam,BEX, Method of fabrication of a microstructure having an internal cavity.
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Ma Manny K. F., Method of making a structure for providing signal isolation and decoupling in an integrated circuit device.
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Michael Featherby ; David J. Strobel ; Phillip J. Layton ; Edward Li, Methods and compositions for ionizing radiation shielding.
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Hierold Christofer,DEX ; Scheiter Thomas,DEX ; Biebl Markus,DEX ; Klose Helmut,DEX, Micromechanical semiconductor component and manufacturing method therefor.
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Kenji Sekine JP; Hiroji Yamada JP; Matsuo Yamasaki JP; Osamu Kagaya JP; Kiichi Yamashita JP, Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate.
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Strobel, David J.; Czajkowski, David R., Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages.
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Czajkowski David ; Eggleston Neil ; Patterson Janet, Radiation shielding of three dimensional multi-chip modules.
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Cadien Kenneth C. (Portland OR) Feller Daniel A. (Portland OR), Slurries for chemical mechanical polishing.
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이 특허를 인용한 특허 (8) 인용/피인용 타임라인 분석

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Mueller, Tyler; Batchelder, Geoffrey; Danzl, Ralph B.; Gerrish, Paul F.; Malin, Anna J.; Marrott, Trevor D.; Mattes, Michael F., Apparatus for restricting moisture ingress.
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Mueller, Tyler; Tyler, Larry E.; Batchelder, Geoffrey; Gerrish, Paul F.; Mattes, Michael F.; Malin, Anna J., Faraday cage for circuitry using substrates.
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Mattes, Michael F.; Ruben, David A., Implantable capacitive pressure sensor apparatus and methods regarding same.
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[미국특허] Shielded structures to protect semiconductor devices 원문보기

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이 특허에 인용된 특허 (17) 인용/피인용 타임라인 분석

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[미국특허] Shielded structures to protect semiconductor devices 원문보기

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이 특허에 인용된 특허 (17) 인용/피인용 타임라인 분석

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