Integrated circuit device and electronic instrument
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/038
G06F-013/14
G09G-005/00
G09G-003/18
G09G-003/36
출원번호
UP-0270551
(2005-11-10)
등록번호
US-7764278
(2010-08-13)
우선권정보
JP-2005-192052(2005-06-30)
발명자
/ 주소
Kumagai, Takashi
Ishiyama, Hisanobu
Maekawa, Kazuhiro
Ito, Satoru
Fujise, Takashi
Karasawa, Junichi
Kodaira, Satoru
Maki, Katsuhiko
출원인 / 주소
Seiko Epson Corporation
대리인 / 주소
Oliff & Berridge, PLC
인용정보
피인용 횟수 :
3인용 특허 :
70
초록▼
An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side,
An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.
대표청구항▼
What is claimed is: 1. An integrated circuit device, comprising: first to Nth circuit blocks (N is an integer larger than one) disposed along a first direction, the first direction being a direction from a first side of the integrated circuit device toward a third side that is opposite to the first
What is claimed is: 1. An integrated circuit device, comprising: first to Nth circuit blocks (N is an integer larger than one) disposed along a first direction, the first direction being a direction from a first side of the integrated circuit device toward a third side that is opposite to the first side, a second direction being a direction from a second side of the integrated circuit device toward a fourth side that is opposite to the second side, the second side being longer than the first side, the first to Nth circuit blocks including first to Ith memory blocks (I is an integer larger than one) that store image data, and first to Ith data driver blocks that drives data lines through which the image data read from the first to Ith memory blocks are supplied to pixels each of which includes an electro-optical element, each of the first to Ith data driver blocks being disposed adjacent to a corresponding memory block among the first to Ith memory blocks along the first direction, the first to Ith memory blocks including a memory cell array, a row address decoder, a column address decoder, and a write/read circuit, write/read processing of the memory cell array being controlled by using the row address decoder, the column address decoder, and the write/read circuit, a Jth data driver block (1≦J<I) among the first to Ith data driver blocks being disposed adjacently on a third direction side of a Jth memory block among the first to Ith memory blocks, the third direction being a direction opposite to the first direction, a (J+1)th data driver block among the first to Ith data driver blocks being disposed adjacently on the first direction side of the Jth memory block, and a (J+1)th memory block among the first to Ith memory blocks being disposed adjacently on the first direction side of the (J+1)th data driver block. 2. The integrated circuit device as defined in claim 1 a column address decoder being used in common by the Jth memory block and the (J+1)th memory block. 3. The integrated circuit device as defined in claim 1, wordlines connected to memory cells of the first to Ith memory blocks being disposed along the second direction in the first to Ith memory blocks, and bitlines through which image data stored in the first to Ith memory blocks is output to the first to Ith data driver blocks being disposed along the first direction in the first to Ith memory blocks. 4. The integrated circuit device as defined in claim 3, data signal output lines of the first to Ith data driver blocks being disposed along the second direction in the first to Ith data driver blocks. 5. The integrated circuit device as defined in claim 3, the first to Ith data driver blocks including a plurality of data drivers disposed along the first direction. 6. An electronic instrument, comprising: the integrated circuit device as defined in claim 3; and the pixels driven by the integrated circuit device. 7. The integrated circuit device as defined in claim 1, data signal output lines of the first to Ith data driver blocks being disposed along the second direction in the first to Ith data driver blocks. 8. The integrated circuit device as defined in claim 1, image data stored in the first to Ith memory blocks being read from the first to Ith memory blocks into the first to Ith data driver blocks a plurality of times in one horizontal scan period. 9. The integrated circuit device as defined in claim 8, the image data stored in the first to Ith memory blocks being read a plurality of times in one horizontal scan period by selecting different wordlines in the first to Ith memory blocks in one horizontal scan period. 10. The integrated circuit device as defined in claim 8, when the number of the pixels in a horizontal scan direction is denoted by HPN, the number of bits of image data for one pixel is denoted by PDB, the number of the first to Ith memory blocks is denoted by MBN, and the number of readings of image data from the first to Ith memory blocks in one horizontal scan period is denoted by RN, a sense amplifier block of the first to Ith memory blocks includes P sense amplifiers arranged along the second direction, P being the number of the sense amplifiers given by (HPN×PDB)/(MBN×RN). 11. An electronic instrument, comprising: the integrated circuit device as defined in claim 8; and the pixels driven by the integrated circuit device. 12. The integrated circuit device as defined in claim 1, the first to Ith data driver blocks including a plurality of data drivers disposed along the first direction. 13. The integrated circuit device as defined in claim 1, when the number of the pixels in a horizontal scan direction is denoted by HPN, the number of bits of image data for one pixel is denoted by PDB, the number of the first to Ith memory blocks is denoted by MBN, and the number of readings of image data from the first to Ith memory blocks in one horizontal scan period is denoted by RN, a sense amplifier block of the first to Ith memory blocks includes P sense amplifiers arranged along the second direction, P being the number of the sense amplifiers given by (HPN×PDB)/(MBN×RN). 14. The integrated circuit device as defined in claim 1, comprising: a first interface region provided along the fourth side and on the second direction side of the first to Nth circuit blocks; and a second interface region provided along the second side and on a fourth direction side of the first to Nth circuit blocks, the fourth direction being opposite to the second direction. 15. The integrated circuit device as defined in claim 14, data signal output lines of the data driver block being disposed in the first interface region along the first direction. 16. An electronic instrument, comprising: the integrated circuit device as defined in claim 14; and the pixels driven by the integrated circuit device. 17. An electronic instrument, comprising: the integrated circuit device as defined in claim 1; and the pixels driven by the integrated circuit device. 18. An integrated circuit device, comprising: first to Nth circuit blocks (N is an integer larger than one) disposed along a first direction, the first direction being a direction from a first side of the integrated circuit device toward a third side that is opposite to the first side, a second direction being a direction from a second side of the integrated circuit device toward a fourth side that is opposite to the second side, the second side being longer than the first side, the first to Nth circuit blocks including at least one memory block that stores image data, and at least one data driver block that drives data lines through which the image data read from the at least one memory block are supplied to pixels each of which includes an electro-optical element, the at least one memory block including a memory cell array, a row address decoder, a column address decoder, and a write/read circuit, write/read processing of the memory cell array being controlled by using the row address decoder, the column address decoder, and the write/read circuit, and the at least one memory block and the at least one data driver block being disposed adjacent to each other along the first direction, when the number of the pixels in a horizontal scan direction is denoted by HPN, the number of bits of image data for one pixel is denoted by PDB, the number of the at least one memory blocks is denoted by MBN, and the number of readings of image data from the at least one memory block in one horizontal scan period is denoted by RN, a sense amplifier block of the at least one memory block includes P sense amplifiers arranged along the second direction, P being the number of the sense amplifiers given by (HPN×PDB)/(MBN×RN). 19. An integrated circuit device, comprising: first to Nth circuit blocks (N is an integer larger than one) disposed along a first direction, the first direction being a direction from a first side of the integrated circuit device toward a third side that is opposite to the first side, a second direction being a direction from a second side of the integrated circuit device toward a fourth side that is opposite to the second side, the second side being longer than the first side, the first to Nth circuit blocks including at least one memory block that stores image data, and at least one data driver block that drives data lines through which the image data read from the at least one memory block are supplied to pixels each of which includes an electro-optical element, the at least one memory block including a memory cell array, a row address decoder, a column address decoder, and a write/read circuit, write/read processing of the memory cell array being controlled by using the row address decoder, the column address decoder, and the write/read circuit, and the at least one memory block and the at least one data driver block being disposed adjacent to each other along the first direction, image data stored in the at least one memory block being read from the at least one memory block into the at least one data driver block a plurality of times in one horizontal scan period, when the number of the pixels in a horizontal scan direction is denoted by HPN, the number of bits of image data for one pixel is denoted by PDB, the number of the at least one memory blocks is denoted by MBN, and the number of readings of image data from the at least one memory block in one horizontal scan period is denoted by RN, a sense amplifier block of the at least one memory block includes P sense amplifiers arranged along the second direction, P being the number of the sense amplifiers given by (HPN×PDB)/(MBN×RN).
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (70)
Keeth, Brent; Bunker, Layne G.; Derner, Scott J., 256 Meg dynamic random access memory.
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of lo.
Voss Peter H. (Eindhoven NLX) Pfennings Leonardus C. M. G. (Eindhoven NLX) O\Connell Cormac M. (Eindhoven NLX) Davies Thomas J. (Eindhoven NLX) Ontrop Hans (Eindhoven NLX) Phelan Cathal G. (Eindhoven, Fast static random access memory with high storage capacity.
Deering Michael F. (Los Altos CA) Schlapp Stephen A. (San Jose CA) Lavelle Michael G. (Saratoga CA), Flexible dram access in a frame buffer memory and system.
Butler Edward (Richmond VT) Goodwin Robert B. (Colchester VT) Shah Hemen R. (Essex ; Jct VT) Tamlyn Robert (Jerico VT), High performance extended data out.
Felton Bradley,GBX ; Chan Albert ; Shen Ju ; Tsui Cyrus Y. ; Camarota Rafael C., Programmable integrated circuit device with slew control and skew control.
Aoyama Yasuhiro,JPX ; Oota Kiyoto,JPX ; Shimakawa Kazuhiko,JPX, Semiconductor device with a metal layer for supplying a predetermined potential to a memory cell section.
Nakamura Hironori,JPX, Semiconductor electrically erasable and programmable read only memory device for concurrently writing data bits into memory cells selected from sectors and method for controlling the multi-write oper.
Inoue Kazunari,JPX ; Matsuoka Hideto,JPX, Semiconductor integrated circuit device allowing fast rewriting of image data and image data processing system using the.
Pinkham Raymond (Missouri City TX) Valente Fredrick A. (Houston TX) Guttag Karl M. (Houston TX) Vanaken Jerry R. (Houston TX), Video serial accessed memory with midline load.
Shin, Chang-Hee; Cho, Ki-Seok; Oh, Kwon-Young, Memory device with one-time programmable function, and display driver IC and display device with the same.
Shin, Chang-Hee; Cho, Ki-Seok; Oh, Kwon-Young, Memory device with one-time programmable function, and display driver IC and display device with the same.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.