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A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum

A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

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Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 1. A method for fabricating an image sensor array of pixels comprising: forming a corresponding light sensitive element in a semiconductor substrate for each array pixel, said element adapted to re

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 1. A method for fabricating an image sensor array of pixels comprising: forming a corresponding light sensitive element in a semiconductor substrate for each array pixel, said element adapted to receive light incident to a respective pixel, said forming step further including the step of forming a structure of insulator material in said substrate above said light sensitive element at each pixel, forming a first interlevel dielectric layer formed atop said substrate; forming a barrier material layer between said substrate and said first interlevel dielectric layer; forming at least one metal interconnect layer formed atop said first interlevel dielectric layer, said formed metal interconnect layer including a Cu metal wire structure formed between each light sensitive element in said array; and forming a second interlevel dielectric layer atop said Cu metal interconnect layer in said array, wherein said Cu metal interconnect layer enables formation of thin first and second interlevel dielectric layers to shorten an optical path and thereby increase an amount of light received by each light sensitive element in said array, and said method further comprising the step of selectively removing portions of said barrier material layer above said substrate at a region corresponding to said insulator material structure formed above said light sensitive element at each pixel. 2. The method as claimed in claim 1, wherein said step of forming a metal interconnect layer including a Cu metal wire structure formed at locations between each light sensitive element in said array comprises: applying a mask over said first interlevel dielectric layer, said mask patterned to open up trenches between each photodiode in said first interlevel dielectric layer; conducting an etch process to open up said trenches at said locations between each photodiode; and, depositing Cu metal in said trenches to form said metal wire structures. 3. The method as claimed in claim 2, wherein said step of forming a metal interconnect layer further comprises the step of conducting a chemical-mechanical polishing step of said metal wire structures. 4. The method as claimed in claim 3, further comprising the step of forming a barrier material layer on top each said Cu metal wire structure of said metal interconnect layer, said forming including implementing a self-aligned process to deposit said barrier material layer on top each formed said Cu metal wire structure of said metal interconnect layer. 5. The method as claimed in claim 4, wherein said step of depositing in a self-aligned process a barrier material on top each said Cu metal wire structure further comprises performing an electroless plating process. 6. The method as claimed in claim 5, wherein said barrier material deposited in said electroless plating process comprises NiWP, CoWP or CoWB. 7. The method as claimed in claim 1, further comprising the steps of: forming a barrier material layer on top said Cu metal wire structures of said metal interconnect layer by blanket depositing a barrier material layer atop said Cu metal wire structures and atop said first interlevel dielectric layer thereby traversing an optical path of each array pixel. 8. The method as claimed in claim 7, further including the step of selectively removing portions of said barrier material layer at regions in line with an optical path of each pixel of said array. 9. The method as claimed in claim 8, wherein said step of selectively removing portions of said barrier material layer at regions in line with an optical path comprises, after blanket depositing said barrier material layer, the steps of: applying a mask structure lithographically patterned to open up regions of said barrier material layer at locations traversing said optical path of each pixel; and conducting an etch process to remove the barrier material layer at said regions. 10. The method as claimed in claim 8, wherein said step of selectively removing portions of said barrier material layer at regions in line with an optical path comprises, after forming a second interlevel dielectric layer atop said Cu metal interconnect layer in said array, the steps of: applying a mask structure lithographically patterned to open up holes at locations traversing said optical path of each pixel; conducting an etch process to selectively remove portions of the second interlevel dielectric layer and barrier material layer portions at said regions; and, refilling interlevel dielectric material back into holes created by said etch. 11. The method as claimed in claim 8, wherein said image sensor array further comprises a top metallization layer formed beneath a color filter array and comprising a metal bonding structure formed between each photodiode in said array, said step of selectively removing portions of said barrier material layer at regions in line with an optical path comprises, after forming said top metallization layer in said array, the steps of: conducting an etch process utilizing said metal bonding structures of said top metallization layer as a self-aligned mask to selectively remove portions of the second interlevel dielectric layer and barrier material layer portions at said regions traversing said optical path of each pixel; and, refilling interlevel dielectric material back into holes created by said etch. 12. The method as claimed in claim 10, wherein said step of conducting an etch process to selectively remove portions of the second interlevel dielectric layer and barrier material layer portions at said regions traversing said optical path of each pixel further includes etching to remove a portion of said first interlevel dielectric layer at said regions to open up a hole corresponding to said pixel optical path, wherein prior to said refilling step, the step of: depositing a thin liner of light reflective material that conforms to the sidewalls of the etched hole. 13. The method as claimed in claim 11, wherein said step of conducting an etch process to selectively remove portions of the second interlevel dielectric layer and barrier material layer portions at said regions traversing said optical path of each pixel further includes etching to remove a portion of said first interlevel dielectric layer at said regions to open up a hole corresponding to said pixel optical path, wherein prior to said refilling step, the step of: depositing a thin liner of light reflective material that conforms to the sidewalls of the etched hole. 14. The method as claimed in claim 1, further comprising a step of forming a top layer comprising an array of filter elements, each filter element corresponding to an array pixel. 15. The method as claimed in claim 14, further comprising a step of forming an array of pixel microlens on said top layer in alignment with said array of filter elements, with each microlens corresponding to a filter element. 16. A method for fabricating an image sensor array of pixels comprising the steps of: forming a corresponding light sensitive element in a semiconductor substrate for each array pixel, said element adapted to receive incident light, said forming further includes the step of forming a structure of insulator material in said substrate above said light sensitive element at each pixel; and forming a stack of interlevel dielectric layers atop said substrate, forming a barrier material layer between said substrate and a first interlevel dielectric layer of said stack, and between forming of adjacent interlevel dielectric layers of said stack, the steps of: forming a Cu metallization level including a Cu metal wire structure formed between each light sensitive element in said array, wherein said Cu metallization levels enables a thinner stack of interlevel dielectric layers to shorten an optical path and thereby increase amount of light received by each light sensitive element in said array, and said method further comprising the step of selectively removing portions of said barrier material layer above said substrate at a region corresponding to said formed insulator material structure at each pixel. 17. The method as claimed in claim 16, wherein said step of forming Cu metal wire structure of each Cu metallization level includes: applying a mask over an underlying interlevel dielectric layer, said mask patterned to open up trenches in between said pixel locations in said underlying dielectric layer; conducting an etch process to open up said trenches at said locations; and depositing Cu metal in said trenches to form said metal wire structures. 18. The method as claimed in claim 17, wherein said step of depositing Cu metal in said trenches further includes lining said trench with a Cu diffusion barrier material. 19. The method as claimed in claim 17, further comprising the step of forming a barrier material layer on top each said Cu metal wire structure, said forming including implementing a self-aligned process to deposit said barrier material layer on top each formed said Cu metal wire structure of said metal interconnect layer. 20. The method as claimed in claim 19, wherein said step of implementing a self-aligned process to deposit a barrier material on top each said Cu metal wire structure further comprises performing an electroless plating process. 21. The method as claimed in claim 16, further comprising the steps of: forming a barrier material layer on top said Cu metal wire structures of said metal interconnect layer by blanket depositing a thin barrier material layer atop said Cu metal wire structures including its respective underlying interlevel dielectric layer, wherein portions of said blanket deposited thin barrier material layer traverses an optical path of each array pixel. 22. The method as claimed in claim 21, further including the step of selectively removing portions of said thin barrier material layer at regions in line with an optical path of each pixel of said array. 23. The method as claimed in claim 22, wherein said step of selectively removing portions of said thin barrier material layer at regions in line with an optical path comprises, after blanket depositing said thin barrier material layer at each metallization level, the steps of applying a mask structure lithographically patterned to open up regions of said barrier material layer at locations traversing said optical path of each pixel; and conducting an etch process to remove the thin barrier material layer at said regions.