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A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor

A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.

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What is claimed is: 1. An integrated circuit comprising: at least one MOS transistor; and at least one bipolar transistor, wherein a channel of said MOS transistor and a base of said bipolar transistor are simultaneously formed in a common epitaxial layer disposed on a semiconducting surface of a s

What is claimed is: 1. An integrated circuit comprising: at least one MOS transistor; and at least one bipolar transistor, wherein a channel of said MOS transistor and a base of said bipolar transistor are simultaneously formed in a common epitaxial layer disposed on a semiconducting surface of a substrate, said epitaxial layer comprising first and second silicon layers and first and second silicon-germanium layers, wherein said first silicon layer is interposed between said semiconducting surface and said second silicon-germanium layer, wherein said first silicon-germanium layer is interposed between said first and said second silicon layers, and wherein said second silicon layer is interposed between said first and said second silicon-germanium layers; and wherein said first layer of silicon-germanium includes an increasing concentration of dopant; said second layer of silicon includes a decreasing concentration of the same dopant; and the concentration of germanium in the second layer of silicon-germanium is higher than the concentration of germanium in the first layer of silicon-germanium. 2. The integrated circuit of claim 1, wherein said first and said second germanium layers are compressively strained. 3. A method of fabricating an integrated BiCMOS circuit, the circuit including bipolar transistors and CMOS transistors on a substrate, the method comprising: forming a buried oxide layer at bipolar and MOS transistor regions in a semiconductor substrate; in the bipolar transistor region of the substrate, forming a doped buried layer over the buried oxide layer, forming a doped collector region over the doped buried layer, and forming a contact terminal to contact the doped collector region via the doped buried layer; in the MOS transistor region of the substrate, forming a doped well structure; forming isolation regions to isolate active areas of the bipolar and MOS transistor regions; following the above steps, growing a common epitaxial layer over the substrate to form a base layer over the bipolar transistor region and a channel region over the MOS transistor region; the growing of the epitaxial layer including: epitaxially growing a first sublayer of silicon on exposed silicon of the substrate; epitaxially growing a first sublayer of silicon-germanium on the first sublayer of silicon; the first sublayer of silicon-germanium being increasingly doped with a dopant; epitaxially growing a second sublayer of silicon on the first sublayer of silicon-germanium; the second sublayer of silicon being decreasingly doped with the same dopant as the first sublayer of silicon-germanium; and epitaxially growing a second sublayer of silicon-germanium on the second sublayer of silicon; the concentration of germanium in the second sublayer of silicon-germanium being higher than the concentration of germanium in the first sublayer of silicon-germanium. 4. The method of claim 3, comprising the step of forming two epitaxial layers, wherein the dopant of a first epitaxial layer is a P-dopant to form a channel region of an NMOS transistor and a base region of a bipolar NPN transistor; and the dopant of a second epitaxial layer is an N-dopant to form a channel region of a PMOS transistor and a base region of a bipolar PNP transistor. 5. The method of claim 3, wherein the dopant included in the epitaxial layer provides a retrograde channel profile for the MOS transistor. 6. The method of claim 3, including the step of forming a doped emitter for the bipolar transistor diffusing at least into the second sublayer of silicon-germanium. 7. The method of claim 3, wherein the steps of growing the first and the second silicon-germanium sublayers provide said first and said second silicon-germanium sublayers with a compressively strained lattice. 8. The method of claim 4, wherein the P-dopant is boron and the N-dopant is arsenic.