IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0076992
(2008-03-26)
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등록번호 |
US-7776722
(2010-09-06)
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우선권정보 |
JP-2007-132590(2007-05-18) |
발명자
/ 주소 |
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출원인 / 주소 |
- Semiconductor Energy Laboratory Co., Ltd.
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
22 |
초록
▼
In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate havi
In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate having a desired shape even when a step is produced on a surface to be bonded. Between steps on the surface to be bonded, dummy patterns 302 are formed at predetermined intervals, and thus the warp of the substrate to be bonded can be suppressed, the adhesion between the bonded substrates can be ensured, and an SOI layer having a desired shape can be obtained.
대표청구항
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What is claimed is: 1. A manufacturing method of a semiconductor substrate; comprising the steps of: irradiating one surface of a first single crystal semiconductor substrate with ions to form a first embrittlement layer at a predetermined depth from the one surface of the first single crystal semi
What is claimed is: 1. A manufacturing method of a semiconductor substrate; comprising the steps of: irradiating one surface of a first single crystal semiconductor substrate with ions to form a first embrittlement layer at a predetermined depth from the one surface of the first single crystal semiconductor substrate; forming a plurality of first element formation patterns and a first dummy pattern arranged between the plurality of first element formation patterns in the one surface of the first single crystal semiconductor substrate by etching, wherein the plurality of the first element formation patterns and the first dummy pattern are arranged at a predetermined interval; providing a substrate having an insulating surface in order to superpose the first single crystal semiconductor substrate such that the surface of the first single crystal semiconductor substrate, on which the first element formation patterns and the first dummy pattern are formed, is bonded to the insulating surface; and separating the first single crystal semiconductor substrate from the plurality of first element formation patterns and the first dummy pattern by thermal treatment, so that the plurality of first element formation patterns and the first dummy pattern are left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the first single crystal semiconductor substrate and the substrate having the insulating surface are bonded. 2. The manufacturing method of a semiconductor substrate according to claim 1; further comprising the steps of: forming a first silicon oxide film on the one surface of the first single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before forming the plurality of first element formation patterns and the first dummy pattern, wherein the first element formation patterns and the first dummy pattern are bonded to the insulating surface with the first silicon oxide film interposed therebetween. 3. The manufacturing method of a semiconductor substrate according to claim 1, wherein the first element formation patterns and the first dummy pattern are formed by etching the first single crystal semiconductor substrate in regions other than the first element formation patterns and the first dummy pattern, deeper than the first embrittlement layer. 4. The manufacturing method of a semiconductor substrate according to claim 1, wherein the first single crystal semiconductor substrate is etched such that at least a cross-sectional view of each of the first element formation patterns is an inversely tapered shape, and a cross-sectional view of each of the first element formation patterns left on the substrate having the insulating surface is a tapered shape. 5. The manufacturing method of a semiconductor substrate according to claim 1, further comprising a step of removing the first dummy pattern left on the substrate having the insulating surface. 6. A manufacturing method of a thin film transistor having a channel region, a source region, and a drain region using the first element formation pattern of the semiconductor substrate formed by the manufacturing method of the semiconductor substrate according to claim 1. 7. The manufacturing method of a semiconductor substrate according to claim 1, further comprising the steps of: irradiating one surface of a second single crystal semiconductor substrate with ions to form a second embrittlement layer at a predetermined depth from the surface of the second single crystal semiconductor substrate; forming a plurality of second element formation patterns and a second dummy pattern arranged between the plurality of second element formation patterns in the one surface of the second single crystal semiconductor substrate by etching, wherein the plurality of the second element formation patterns and the second dummy pattern are arranged at a predetermined interval; providing the substrate having the insulating surface on which at least the first element formation patterns are left in order to superpose the second single crystal semiconductor substrate such that the surface of the second single crystal semiconductor substrate, on which the second element formation patterns and the second dummy pattern are formed, is bonded to the insulating surface, wherein said bonding is conducted so as not to overlap the first element formation patterns or the first dummy pattern with the second element formation patterns or the second dummy pattern; and separating the second single crystal semiconductor substrate from the plurality of second element formation patterns and the second dummy pattern; that are left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the second single crystal semiconductor substrate and the substrate having the insulating surface are bonded. 8. The manufacturing method of a semiconductor substrate according to claim 7, further comprising the steps of: forming a second silicon oxide film on the one surface of the second single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before forming the plurality of second element formation patterns and the second dummy pattern, wherein the second element formation patterns and the second dummy pattern are bonded to the insulating surface with the second silicon oxide film interposed therebetween. 9. The manufacturing method of a semiconductor substrate according to claim 7, wherein the second element formation patterns and the second dummy pattern are formed by etching the second single crystal semiconductor substrate in regions other than the second element formation patterns and the second dummy pattern, deeper than the second embrittlement layer. 10. The manufacturing method of a semiconductor substrate according to claim 7, wherein the second single crystal semiconductor substrate is etched such that at least a cross-sectional view of each of the second element formation patterns is an inversely tapered shape, and a cross-sectional view of each of the second element formation patterns left on the substrate having the insulating surface is a tapered shape. 11. The manufacturing method of a semiconductor substrate according to claim 7, wherein the thicknesses of the second element formation patterns and the second dummy pattern are larger than those of the first element formation patterns and the first dummy pattern. 12. The manufacturing method of a semiconductor substrate according to claim 7, further comprising a step of removing the second dummy pattern left on the substrate having the insulating surface. 13. The manufacturing method of a semiconductor substrate according to claim 7, wherein a crystal face of a surface of the first single crystal semiconductor substrate is different from a crystal face of a surface of the second single crystal semiconductor substrate. 14. The manufacturing method of a semiconductor substrate according to claim 13, wherein one of the different crystal faces is {100} and the other is {110}. 15. A manufacturing method of a semiconductor device according to claim 14 further comprising: forming an n-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {100}, and forming a p-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {110}. 16. A manufacturing method of a semiconductor device according to claim 14 further comprising: forming a p-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {110}, and forming an n-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {100}. 17. A manufacturing method of a semiconductor substrate, comprising the steps of: irradiating one surface of a first single crystal semiconductor substrate with ions to form a first embrittlement layer at a predetermined depth from the surface of the first single crystal semiconductor substrate; providing a substrate having an insulating surface in order to superpose the first single crystal semiconductor substrate such that the one surface of the first single crystal semiconductor substrate is bonded to the insulating surface; separating the first single crystal semiconductor substrate from a single crystal semiconductor layer by thermal treatment, so that the single crystal semiconductor layer is left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the first single crystal semiconductor substrate and the substrate having the insulating surface are bonded; etching the single crystal semiconductor layer to form a plurality of first element formation patterns; irradiating one surface of a second single crystal semiconductor substrate with ions to form a second embrittlement layer at a predetermined depth from the surface of the second single crystal semiconductor substrate; forming a plurality of second element formation patterns and a dummy pattern arranged between the plurality of second element formation patterns in the one surface of the second single crystal semiconductor substrate by etching, wherein the plurality of second element formation patterns and the dummy pattern are arranged at a predetermined interval; providing the substrate having the insulating surface on which the first element formation patterns are left in order to superpose the second single crystal semiconductor substrate such that the surface of the second single crystal semiconductor substrate, on which the second element formation patterns and the dummy pattern are formed, is bonded to the insulating surface, wherein said bonding is conducted so as not to overlap the first element formation patterns with the second element formation patterns or the dummy pattern; and separating the second single crystal semiconductor substrate from the plurality of second element formation patterns and the dummy pattern; that are left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the second single crystal semiconductor substrate and the substrate having the insulating surface are bonded. 18. A manufacturing method of a semiconductor substrate, comprising the steps of: irradiating one surface of a first single crystal semiconductor substrate with ions to form a first embrittlement layer at a predetermined depth from the surface of the first single crystal semiconductor substrate; providing a substrate having an insulating surface in order to superpose the first single crystal semiconductor substrate such that the one surface of the first single crystal semiconductor substrate is bonded to the insulating surface; separating the first single crystal semiconductor substrate from a single crystal semiconductor layer by thermal treatment, so that the single crystal semiconductor layer is left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the first single crystal semiconductor substrate and the substrate having the insulating surface are bonded; etching the single crystal semiconductor layer to form a plurality of first element formation patterns and a dummy pattern formed between the plurality of first element formation patterns, wherein the plurality of the first element formation patterns and the dummy patterns are arranged at a predetermined interval; irradiating one surface of a second single crystal semiconductor substrate with ions to form a second embrittlement layer at a predetermined depth from the surface of the second single crystal semiconductor substrate; forming a plurality of second element formation patterns in the one surface of the second single crystal semiconductor substrate by etching; providing the substrate having the insulating surface on which the first element formation patterns and the dummy pattern are left in order to superpose the second single crystal semiconductor substrate such that the surface of the second single crystal semiconductor substrate, on which the second element formation patterns are formed, is bonded to the insulating surface, wherein said bonding is conducted so as not to overlap the first element formation patterns or the dummy pattern with the second element formation patterns; and separating the second single crystal semiconductor substrate from the plurality of second element formation patterns; that are left on the substrate having the insulating surface, wherein the thermal treatment is performed in a state that the second single crystal semiconductor substrate and the substrate having the insulating surface are bonded. 19. The manufacturing method of a semiconductor substrate according to claim 17; further comprising the steps of: forming a first silicon oxide film on the one surface of the first single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before the first single crystal semiconductor substrate is bonded to the insulating surface; and forming a second silicon oxide film on the one surface of the second single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before forming the plurality of second element formation patterns and the dummy pattern, wherein the first element formation patterns are bonded to the insulating surface with the first silicon oxide film interposed therebetween, and wherein the second element formation patterns and the dummy pattern are bonded to the insulating surface with the second silicon oxide film interposed therebetween. 20. The manufacturing method of a semiconductor substrate according to claim 18; further comprising the steps of: forming a first silicon oxide film on the one surface of the first single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before the first single crystal semiconductor substrate is bonded to the insulating surface; and forming a second silicon oxide film on the one surface of the second single crystal semiconductor substrate by a chemical vapor deposition method using a silane-based gas before forming the plurality of second element formation patterns, wherein the first element formation patterns and the dummy pattern are bonded to the insulating surface with the first silicon oxide film interposed therebetween, and wherein the second element formation patterns are bonded to the insulating surface with the second silicon oxide film interposed therebetween. 21. The manufacturing method of a semiconductor substrate according to claim 17, wherein the second element formation patterns and the dummy pattern are formed by etching the second single crystal semiconductor substrate in regions other than the second element formation patterns and the dummy pattern, deeper than the second embrittlement layer. 22. The manufacturing method of a semiconductor substrate according to claim 18, wherein the second element formation patterns are formed by etching the second single crystal semiconductor substrate in regions other than the second element formation patterns, deeper than the second embrittlement layer. 23. The manufacturing method of a semiconductor substrate according to claim 17, wherein the thicknesses of the second element formation patterns and the dummy pattern are larger than those of the first element formation patterns. 24. The manufacturing method of a semiconductor substrate according to claim 17, further comprising a step of removing the dummy pattern left on the substrate having the insulating surface. 25. The manufacturing method of a semiconductor substrate according to claim 18, further comprising a step of removing the dummy pattern left on the substrate having the insulating surface. 26. The manufacturing method of a semiconductor substrate according to claim 17, wherein the second single crystal semiconductor substrate is etched such that at least a cross-sectional view of each of the second element formation patterns is an inversely tapered shape, and a cross-sectional view of each of the second element formation patterns left on the substrate having the insulating surface is a tapered shape. 27. The manufacturing method of a semiconductor substrate according to claim 18, wherein the second single crystal semiconductor substrate is etched such that at least a cross-sectional view of each of the second element formation patterns is an inversely tapered shape, and a cross-sectional view of each of the second element formation patterns left on the substrate having the insulating surface is a tapered shape. 28. The manufacturing method of a semiconductor substrate according to claim 17, wherein a crystal face of a surface of the first single crystal semiconductor substrate is different from a crystal face of a surface of the second single crystal semiconductor substrate. 29. The manufacturing method of a semiconductor substrate according to claim 18, wherein a crystal face of a surface of the first single crystal semiconductor substrate is different from a crystal face of a surface of the second single semiconductor substrate. 30. The manufacturing method of a semiconductor substrate according to claim 28, wherein one of the different crystal faces is {100} and the other is {110}. 31. The manufacturing method of a semiconductor substrate according to claim 29, wherein one of the different crystal faces is {100} and the other is {110}. 32. A manufacturing method of a semiconductor device according to claim 30 further comprising: forming an n-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {100}, and forming a p-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {110}. 33. A manufacturing method of a semiconductor device according to claim 30 further comprising: forming a p-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {110}, and forming an n-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {100}. 34. A manufacturing method of a semiconductor device according to claim 31 further comprising: forming an n-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {100}, and forming a p-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {110}. 35. A manufacturing method of a semiconductor device according to claim 31 further comprising: forming a p-channel thin film transistor using the first element formation pattern formed from the first single crystal semiconductor substrate having the crystal face {110}, and forming an n-channel thin film transistor using the second element formation pattern formed from the second single crystal semiconductor substrate having the crystal face {100}.
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