[특허]Method and system for latchup suppression

[미국특허] Method and system for latchup suppression 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-017/16 H03K-019/003 H03K-003/00
출원번호	UP-0241552 (2005-09-30)
등록번호	US-7786756 (2010-09-20)
발명자 / 주소	Svilan, Vjekoslav Chen, Tien-Min Koniaris, Kleanthes G. Burr, James B.
인용정보	피인용 횟수 : 4 인용 특허 : 84

초록 ▼

Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.

대표청구항 ▼

What is claimed is: 1. A latchup suppression system comprising: a voltage supply configured for applying a voltage to a body terminal of a semiconductor device; a selective coupling mechanism configured to selectively isolate the body terminal from the voltage-supply responsive to a reference voltage exceeding the voltage at the body terminal; and a voltage comparator configured to compare the voltage at body terminal to the reference voltage, and configured to control the selective coupling mechanism. 2. The latchup suppression system of claim 1, wherein the voltage comparator and the selective coupling mechanism are configured to be controlled independently of the voltage supply. 3. The latchup suppression system of claim 2 wherein the selective coupling mechanism is configured to couples the body terminal to the voltage supply responsive to the body terminal voltage exceeding the reference voltage. 4. The latchup suppression system of claim 1 wherein the selective coupling is configured to not interrupt operation of the voltage supply. 5. The latchup suppression system of claim 1 embedded in an integrated circuit. 6. The latchup suppression system of claim 5 wherein the integrated circuit comprises a microprocessor. 7. A latchup suppression system comprising: a voltage comparator for generating a first control voltage responsive to a relationship of a voltage applied to a body terminal of a semiconductor device and a reference voltage; a plurality of selective coupling transistors for selectively coupling said body terminal to a respective power supply; and a level shifting circuit for accessing said first control voltage to produce a second control voltage for controlling said plurality of selective coupling transistors. 8. The latchup suppression system of claim 7 wherein the voltage comparator, the plurality of selective coupling transistors and the level shifting circuit are configured to be controlled independently of a voltage supply configured to apply a voltage to the body terminal. 9. The latchup suppression system of claim 8 wherein said plurality of selective coupling transistors couples said body terminal to said respective power supply responsive to said body terminal voltage exceeding said reference voltage. 10. The latchup suppression system of claim 8 wherein said plurality of selective coupling transistors isolates said body terminal from said respective power supply responsive to said reference voltage exceeding said body terminal voltage. 11. The latchup suppression system of claim 7 wherein said second control voltage is for turning said plurality of selective coupling transistors substantially fully off when said body terminal is at less than a ground potential. 12. The latchup suppression system of claim 7 wherein a lower voltage rail of said level shifting circuit is coupled to said body terminal. 13. The latchup suppression system of claim 7 wherein said level shifting circuit is selectively coupled to one of at least two operating voltages. 14. A method of suppressing latchup in an integrated circuit comprising: comparing a body biasing voltage of a body terminal to a desirable reference voltage; and responsive to said comparing, selectively isolating said body terminal from a respective power supply. 15. The method of claim 14 wherein said body terminal is coupled to a p-type well of said integrated circuit. 16. The method of claim 15 wherein said coupling is responsive to said reference voltage exceeding said body biasing voltage. 17. The method of claim 14 wherein said body terminal is coupled to an n-type well of said integrated circuit. 18. The method of claim 17 wherein said coupling is responsive to said body biasing voltage dropping below said reference voltage. 19. The method of claim 14 further comprising commanding a reference voltage supply to generate said desirable reference voltage. 20. The method of claim 14 further comprising isolating said body terminal from said respective power supply responsive to a change in a condition of said comparing. 21. A method of changing body bias of a semiconductor device comprising: isolating a body terminal of the semiconductor device; comparing a voltage of the body terminal to a reference voltage; and responsive to said comparing, selectively coupling the body terminal to a respective power supply. 22. The method of claim 21 wherein the body terminal is coupled to a p-type well of said semiconductor device. 23. The method of claim 22 wherein said coupling is responsive to the reference voltage exceeding the body biasing voltage. 24. The method of claim 21 wherein the body terminal is coupled to an n-type well of the semiconductor device. 25. The method of claim 24 wherein said coupling is responsive to the body biasing voltage dropping below the reference voltage. 26. The method of claim 21 further comprising commanding a reference voltage supply to generate the reference voltage. 27. The method of claim 21 wherein the reference voltage corresponds to a forward bias condition of the semiconductor device. 28. A latchup suppression system comprising: a voltage supply means configured to apply a voltage to a body terminal of a metal oxide semiconductor field effect transistor (MOSFET); a selective coupling means configured to selectively couple the body terminal to a respective power supply means responsive to the body terminal voltage exceeding a reference voltage; and a voltage comparator means configured to compare the voltage applied to the body terminal of the MOSFET to the reference voltage, and configured to control the selective coupling means and wherein the voltage comparator means and the selective coupling means are configured to be controlled independently of the voltage supply configured for applying a voltage to the body terminal of the MOSFET. 29. The latchup suppression system of claim 28 wherein the selective coupling means is configured to isolate the body terminal of the MOSFET from the respective power supply means responsive to the reference voltage exceeding the body terminal voltage. 30. The latchup suppression system of claim 28 wherein the selective coupling means is configured to not interrupt operation of the voltage supply means for applying a voltage to the body terminal. 31. The latchup suppression system of claim 28 embedded in an integrated circuit. 32. The latchup suppression system of claim 31 wherein the integrated circuit comprises a microprocessor. 33. A latchup suppression system comprising: a voltage comparator means for generating a first control voltage responsive to a relationship of a voltage applied to a body terminal of a semiconductor device and a reference voltage; a plurality of selective coupling transistor means for selectively coupling the body terminal to a respective power supply means; and a level shifting circuit means coupled to receive the first control voltage and for producing a second control voltage for controlling the plurality of selective coupling transistor means. 34. The latchup suppression system of claim 33 wherein the voltage comparator means, the plurality of selective coupling transistor means and the level shifting circuit means are configured to be controlled independently of a voltage supply means configured to apply a voltage to the body terminal. 35. The latchup suppression system of claim 34 wherein the plurality of selective coupling transistor means couples the body terminal to the respective power supply means responsive to the body terminal voltage exceeding the reference voltage. 36. The latchup suppression system of claim 34 wherein the plurality of selective coupling transistor means isolates the body terminal the respective power supply means responsive to the body terminal voltage exceeding the reference voltage. 37. The latchup suppression system of claim 33 wherein the second control voltage is for turning the plurality of selective coupling transistor means substantially fully off when the body terminal is at less than ground potential. 38. The latchup suppression system of claim 33 wherein a lower voltage rail of said level shifting circuit means is coupled to the body terminal.

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