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Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a

Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

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We claim: 1. A semiconductor integrated circuit (IC) package comprising: a substrate having a first surface and a second surface located on each side of a core portion with the core portion including a stripline having a signal plane and a pair of reference planes each arranged on different layers

We claim: 1. A semiconductor integrated circuit (IC) package comprising: a substrate having a first surface and a second surface located on each side of a core portion with the core portion including a stripline having a signal plane and a pair of reference planes each arranged on different layers of the substrate core, the pair of reference planes including a power plane, and a ground plane each defined by a planar layer of conductive material arranged such that the signal plane is positioned between the pair of reference planes of the stripline, the signal plane having an electrical signal trace extending a first length across the signal plane and arranged in between the pair of reference planes such that one of the reference planes extends contiguously above a substantial portion of the first length of the signal trace and such that another of the reference planes extends contiguously under a substantial portion of the first length of the signal trace enabling the plurality of electrical signal traces to be shielded by the ground plane and the power plane of the stripline; an integrated circuit die mounted to a first surface of the substrate; and a discrete non-active electrical component mounted on the first surface of the substrate so that the integrated circuit die is electrically connected with the discrete non-active electrical component through the electrical signal trace of the package and wherein the discrete non-active electrical component is also electrically connected with an I/O (input/output) solder ball arranged on the second surface of the substrate said connection facilitated by a conductive via that passes through the core portion of the substrate. 2. The package of claim 1 wherein the discrete non-active electrical component is mounted relatively close to the die and not near an edge of the substrate. 3. The package of claim 1 wherein the discrete non-active electrical component comprises a capacitive element that operates as an AC coupling capacitor. 4. The IC package of claim 1 wherein the substrate is arranges so that said one of the reference planes that extends contiguously above a substantial portion of the first length of the signal trace is configured so that extends contiguously over substantially all of the of the first length of the signal trace and such that the another reference plane extends contiguously under substantially all of the first length of the signal trace. 5. An electronic device incorporating the IC package of claim 4 wherein the electronic device comprises a computer device. 6. A semiconductor integrated circuit (IC) package comprising: a substrate having a first surface and a second surface located on opposites sides of a core portion with the core portion including; a stripline having, a pair of reference planes comprising a power plane and a ground plane; the power plane comprising a single layer of planar conductive material arranged to provide power, the ground plane comprising a single layer of planar conductive material arranged to provide grounding, and a signal layer having a first signal line having a first length arranged between the reference planes such that one of the reference planes extends contiguously above a substantial portion of the first length of the first signal line and such that another of the reference planes extends contiguously under a substantial portion of the first length of the first signal line enabling the first signal line to be shielded by the ground plane and the power plane of the stripline; an integrated circuit die mounted to a first surface of the substrate; and a discrete non-active electrical component mounted on the first surface of the substrate; and a connection path, that defines an electrical conduction path between said die and the discrete non-active electrical component and between the component and an I/O (input/output) solder ball arranged on the second surface of the substrate, said path including a conductive first via that passes through the core portion of the substrate. 7. The IC package of claim 6 wherein the conductive first via passes through an aperture in the planar conductive material of at least one of said ground plane and said power plane. 8. The IC package of claim 7 wherein the first surface of the substrate has formed thereon a pattern of surface mounted conductive traces, portions of said traces form a portion of the connection path wherein a trace defines the electrical conduction path between said die and the discrete non-active electrical component and another trace defines the electrical conduction path between said component and the first via, said first via connecting the another trace with the an I/O solder ball on the second surface of the substrate. 9. The IC package of claim 8 wherein the discrete non-active electrical component is mounted close to said die. 10. An IC package comprising; a layered substrate including a top surface and a bottom surface with a core arranged therebetween, the substrate further including, an IC mounting portion arranged on the top surface, a plurality of solder balls arranged on the bottom surface, the core including a plurality of planes including a first plane, a second plane, and a third plane, configured so that, first portions of the first and third planes defining a pair of reference planes, a first portion of the second plane defining a signal plane, the planes arranged so that the first plane is arranged above the second plane and the third plane is arranged below the second plane and such that each of the planes are separated from each other by regions of insulating material of the core, the pair of reference planes comprise a ground plane and a power plane, and a stripline region having a stripline structure comprising, a signal line extending a first length across the signal plane, a ground line having a ground line length extending across the ground plane in a same direction as the first length of the signal line and arranged in one of: directly above the signal line or directly below the signal line, and a ground line having a ground line length extending across the ground plane in a same direction as the first length of the signal line and arranged in one of: directly above the signal line or directly below the signal line, a power line having a power line length extending along the power plane in a same direction as the first length of the signal line and arranged in another of: directly above the signal line or directly below the signal line and arranged opposite of the signal line from the ground line thereby sandwiching the signal line between the power line and the ground line; an integrated circuit die mounted to IC mounting portion of the substrate; and a discrete non-active electrical component mounted on the top surface of the substrate and electrically connected with the integrated circuit die using the signal line of the stripline and also electrically with one of said solder balls arranged on the bottom surface of the substrate using a conductive via that passes through the core portion of the substrate. 11. The package of claim 10 wherein the conductive via that passes through the core portion of the substrate also passes through an aperture in one of said ground plane and power planes to enable contact with the I/O (input/output) solder ball arranged on the second surface. 12. The package of claim 10, wherein the discrete non-active electrical component is selected from among the group consisting of capacitors, resistors, and inductors. 13. The IC package of claim 10 wherein the package comprises a ball grid array package. 14. The IC package of claim 10 wherein the package comprises a flip chip package. 15. An IC package comprising; a layered substrate including a top surface and a bottom surface with a core arranged therebetween, the substrate further including, an IC mounting portion arranged on the top surface, a plurality of I/O solder balls arranged on the bottom surface, the core including a plurality of planes including a first plane, a second plane, and a third plane each arranged so that the first plane is lies above the second plane and the third plane lies below the second plane and so that each of the planes are separated from each other by regions of insulating material of the core, a stripline region and a microstrip region, the stripline region comprising a stripline structure having, first portions of the first, second, and third planes, each configured such that the first portion of the second plane defining a first signal plane, and the first portions of the first and third planes define a pair of reference planes comprising a first ground plane and a first power plane arranged such that one of the reference planes lies above the signal plane wherein another of the reference planes lies below the signal plane, the stripline structure further comprising, a first signal line extending a first length across the first signal plane, a first ground line having a first ground line length extending across the first ground plane in a same direction as the first signal line, and a first power line having a first power line length extending across the first power plane in a same direction as the first signal line; the microstrip region comprising a microstrip structure having, second portions of the first, second, and third planes, each configured such that the second portion of the first plane defining a second signal plane, and the second portions of the second and third planes define a pair of second reference planes comprising a second ground plane and a second power plane arranged such that both second reference planes lie below the second signal plane, the microstrip structure further comprising, a second signal line extending a second length across the second signal plane, a second ground line having a second ground line length extending across the second ground plane in a same direction as the second signal line, and a second power line having a second power line length extending across the second power plane in a same direction as the second signal line; an integrated circuit die mounted to IC mounting portion of the substrate; and a discrete non-active electrical component mounted on the top surface of the substrate and electrically connected with the integrated circuit die using the signal line of the microstrip and also electrically with one of said solder balls arranged on the bottom surface of the substrate using a conductive via that passes through the core portion of the substrate. 16. A semiconductor integrated circuit (IC) package as recited in claim 15 wherein: the substrate is arranged with the microstrip region located spatially closer to the integrated circuit die mounted on the substrate relative to a more distantly positioned strip line region wherein the close proximity the microstrip region to the integrated circuit die enables the electrical traces of the microstrip to form short conductive paths between the die and the discrete electronic component and wherein longer conduction paths from the discrete component to the I/O solder ball are formed using the shielded electrical traces of the stripline.