[특허]Planarizing probe card

[미국특허] Planarizing probe card 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-031/02
출원번호	UP-0953204 (2007-12-10)
등록번호	US-7791361 (2010-09-27)
발명자 / 주소	Karklin, Ken Garaedian, Raffi
출원인 / 주소	Touchdown Technologies, Inc.
대리인 / 주소	de la Cerra, Manuel F.
인용정보	피인용 횟수 : 4 인용 특허 : 35

초록 ▼

A novel planarizing probe card for testing a semiconductor device is presented. The probe card is adapted to come into contact with a probe card mount that is in adjustable contact with the prober. The probe card includes a printed circuit board affixed to a stiffener and a probe head that is in electrical contact with the printed circuit board. The probe head also includes a plurality of probe contactor tips that define a first plane. The stiffener further contains at least two planarizing adjusters that comes into contact with the probe card mount. The adjusters may be actuated to alter the position of first plane. A surface of the semiconductor device under test may define a second plane, and the adjusters may be adjusted to position the first plane to be substantially parallel to the second plane.

대표청구항 ▼

The invention claimed is: 1. A probe testing apparatus comprising: a prober; a test head; a probe card mount, wherein the probe card mount is attached to the test head, the test head and the probe card mount are in adjustable contact with a prober through a first set of planarizing adjusters; a probe card for testing a semiconductor device, the probe card is in adjustable contact with a probe card mount, the probe card comprising: a printed circuit board affixed to a stiffener, wherein the stiffener provides rigid support to the printed circuit board; a probe head that is in electrical contact with the printed circuit board, the probe head further comprising a plurality of probe contactor tips, the plurality of probe contactor tips defining a first plane; and the stiffener further comprising a second set of planarizing adjusters that come into contact with the probe card mount and wherein the first and second set of adjusters may be actuated to alter the position of first plane. 2. The probe testing apparatus of claim 1, wherein a surface of the semiconductor device defines a second plane, and the first and second set of adjusters position the first plane to be substantially parallel to the second plane. 3. The probe testing apparatus of claim 1, wherein the semiconductor device lies on a probe chuck, and a surface of the probe chuck defines a second plane, and the first and second set of adjusters position the first plane to be substantially parallel to the second plane. 4. The probe testing apparatus of claim 1, wherein a surface of the semiconductor device defines a second plane, and the first and second set of adjusters position the first plane to less than 10 micrometers from parallel of the second plane. 5. The probe testing apparatus of claim 1, wherein each adjusters may be adjusted +/−100 micrometers. 6. The probe testing apparatus of claim 1, wherein the second set of adjusters comprises at least three adjusters spaced at about 120 degrees apart from each other. 7. The probe testing apparatus of claim 1 further comprising an interposer that is in electrical contact with the printed circuit board and the probe head. 8. The probe testing apparatus of claim 1 wherein the probe head further comprises a plurality of cantilever probe contactors. 9. The probe testing apparatus of claim 1 wherein the probe head further comprises a plurality of torsional probe contactors. 10. A probe testing apparatus comprising: a prober; a probe card mount, wherein the probe card mount is in adjustable contact with a prober through a first set of planarizing adjusters; a probe card for testing a semiconductor device, the probe card is in adjustable contact with a probe card mount, the probe card comprising: a stiffener comprising a first stiffener part and a second stiffener part; a printed circuit board affixed to the first stiffener part and the second stiffener part, wherein the stiffener provides rigid support to the printed circuit board; and a second set of planarizing adjusters that may be actuated to alter the position of the first stiffener part relative to the second stiffener part, thereby deflecting the printed circuit board; a probe head that is in electrical contact with the printed circuit board, the probe head further comprising a plurality of probe contactor tips, the plurality of probe contactor tips defining a first plane; the stiffener further comprising a third set of planarizing adjusters that come into contact with the probe card mount; wherein the first, second and third set of planarizing adjusters may be actuated to alter the position of first plane.

이 특허에 인용된 특허 (35) 인용/피인용 타임라인 분석

Mathieu,Gaetan L.; Eldridge,Benjamin N.; Grube,Gary W., Apparatuses and methods for planarizing a semiconductor contactor.
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Kasukabe Susumu,JPX ; Mori Terutaka,JPX ; Ariga Akihiko,JPX ; Shigi Hidetaka,JPX ; Watanabe Takayoshi,JPX ; Kono Ryuji,JPX, Connector and probing system.
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Long Tom (Portland OR) Sabri Mohamed (Beaverton OR) Saunders J. Lynn (Hillsboro OR), Contact device for making connection to an electronic circuit device.
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Elsner Gerhard,DEX ; Greschner Johann,DEX ; Stoehr Roland,DEX, Contact probe arrangement for functional electrical testing.
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Hatada Kenzo (Katano JPX) Ishihara Takeshi (Neyagawa JPX) Suzuki Nobuaki (Osaka JPX) Kuroda Satowaka (Osaka JPX), Device for testing semiconductor integrated circuits and method of testing the same.
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Hembree David R. ; Farnworth Warren M. ; Wark James M., Force applying probe card and test system for semiconductor wafers.
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Whann Welton B. (San Diego CA) Elizondo Paul M. (Escondido CA), High density probe card.
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Ardezzone Frank J. (Santa Clara CA), High density probe-head with isolated and shielded transmission lines.
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Bove Ronald (Wappingers Falls NY) Hubacher Eric M. (Wappingers Falls NY), High density wafer contacting and test system.
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Kiyoshi Takekoshi JP, Inspection stage including a plurality of Z shafts, and inspection apparatus.
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Veenendaal Cornelis T. (Cornelius OR), Integrated circuit probe parallelism establishing method and apparatus.
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Kasukabe Susumu (Yokohama JPX) Takagi Ryuichi (Tokyo JPX), Manufacturing method of a probe head for semiconductor LSI inspection apparatus.
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Liu Ken K. F. (Saratoga CA) Min Byoung-Youl (Cupertino CA) Moti Robert J. (San Jose CA) Husain Syed A. (Milpitas CA), Membrane probing of circuits.
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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
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January Kister ; Jean-Michel Jurin FR; Isabelle George FR, Modulated space transformer for high density buckling beam probe and method for making the same.
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Faure Louis Henry (Poughkeepsie NY) Johnston ; Jr. Howard Thomas (Poughkeepsie NY) Townsend Dana Roberts (Fishkill NY), Multiple site, differential displacement, surface contacting assembly.
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Woith Blake F. (Orange CA), Pivotable self-centering elastomer pressure-wafer probe.
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Nakajima Hisashi (Yamanishi-ken JPX) Yoshioka Haruhiko (Yamanishi-ken JPX), Probe apparatus for correcting the probe card posture before testing.
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Mori, Shigeoki; Karasawa, Wataru, Probe apparatus for probing an object held above the probe card.
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Nakajima Hisashi,JPX ; Yoshioka Haruhiko,JPX, Probe apparatus with tilt correction mechanisms.
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Higgins H. Dan ; Martinez Martin A. ; Bates R. Dennis, Probe assembly and method for switchable multi-DUT testing of integrated circuit wafers.
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Higgins H. Dan (323 E. Redfield Chandler AZ 85225), Probe card apparatus.
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Audette,David M.; Gardell,David L.; Hagios,John F.; Sullivan,Christopher L., Probe card assembly.
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Higgins H. Dan ; Pandey Rajiv ; Armendariz Norman J. ; Bates R. Dennis, Probe card assembly for high density integrated circuits.
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Trenary Dale T. (San Jose CA), Probe card for integrated circuit chip.
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Yu, David; Zhou, Yu; Aldaz, Robert Edward, Probe contact system having planarity adjustment mechanism.
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Zhou, Yu; Yu, David; Aldaz, Robert Edward, Probe contact system having planarity adjustment mechanism.
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Ikeda Towl (Kofu JPX) Koike Hisashi (Yamanashi JPX), Quartz probe apparatus.
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Huff Richard E. (Belmont CA) Matta Farid (Mountain View CA), Self-leveling membrane probe.
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Ryuji Kohno JP; Tetsuo Kumazawa JP; Makoto Kitano JP; Akihiko Ariga JP; Yuji Wada JP; Naoto Ban JP; Shuji Shibuya JP; Yasuhiro Motoyama JP; Kunio Matsumoto JP; Susumu Kasukabe JP; Terutaka , Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step.
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Kim,Kyung Y., Test probe alignment apparatus.
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Evans Arthur (Brookfield Center CT) Baker Joseph R. (New Milford CT) Rising Robert P. (Trumbull CT), Test probe assembly for testing integrated circuit devices.
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Beaman Brian S. (Hyde Park NY) Fogel Keith E. (Bardonia NY) Lauro Paul A. (Nanuet NY) Norcott Maurice H. (Valley Cottage NY) Shih Da-Yuan (Poughkeepsie NY) Walker George F. (New York NY), Test probe having elongated conductor embedded in an elostomeric material which is mounted on a space transformer.
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Jafari, Nasser Ali; Karklin, Kenneth Dean; Sprague, William T., Unified apparatus and method to assure probe card-to-wafer parallelism in semiconductor automatic wafer test, probe card measurement systems, and probe card manufacturing.
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Ieda,Hisashi; Oomura,Mitsuyo, Vehicle power supply control apparatus.
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이 특허를 인용한 특허 (4) 인용/피인용 타임라인 분석

Lewinnek, David Walter; Sinsheimer, Roger Allen; Valiente, Luis Antonio; DiPalo, Craig Anthony, Interconnect for transmitting signals between a device and a tester.
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Audette, David M.; Fregeau, Dustin; Gardell, David L.; Neff, Peter W.; Roy, III, Frederick H.; Wagner, Grant W., Probe card assembly.
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Sinsheimer, Roger Allen, Structure for transmitting signals in an application space between a device under test and test electronics.
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Suto, Anthony J.; Wrinn, Joseph Francis; Toscano, John P.; Arena, John Joseph, Test fixture.
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[미국특허] Planarizing probe card 원문보기

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이 특허에 인용된 특허 (35) 인용/피인용 타임라인 분석

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