IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0268854
(2005-11-08)
|
등록번호 |
US-7795615
(2010-10-04)
|
발명자
/ 주소 |
- Goebel, Thomas
- Kaltalioglu, Erdem
- Kim, Sun-Oo
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
5 인용 특허 :
12 |
초록
▼
An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within
An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
대표청구항
▼
What is claimed is: 1. An integrated circuit comprising: a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip; integrated circuitry within the circuit area, wherein no active circuit is disposed within the peripheral area; and a barri
What is claimed is: 1. An integrated circuit comprising: a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip; integrated circuitry within the circuit area, wherein no active circuit is disposed within the peripheral area; and a barrier within the peripheral area, the barrier at least partially surrounding the circuit area, wherein the barrier comprises: a bottom electrode, a top electrode capacitively coupled to the bottom electrode, and vertically spaced from the bottom electrode, a plurality of metallization layers lying in planes between the top electrode and the bottom electrode, and vias electrically coupling the metallization layers, wherein the vias are shorter in length than conductors in the metallization layers, wherein the length is measured along a line around the circuit area. 2. The integrated circuit of claim 1, wherein a first stack of conductors is formed from a first plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the bottom electrode, and wherein a second stack of conductors is formed from a second plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the top electrode such that at least a portion of a capacitor structure formed by the top and bottom electrodes is formed between the first stack of conductors and the second stack of conductors. 3. The integrated circuit of claim 1, wherein the vias are a same length and width as vias in the circuit area. 4. The integrated circuit of claim 2, wherein the top electrode comprises a conductive plate and wherein the bottom electrode comprises a conductive plate. 5. The integrated circuit of claim 4, wherein each stack of conductors is formed from vertically alternating lines and plates, each line being electrically coupled to a plate above it and a plate below it. 6. The integrated circuit of claim 4, wherein each stack of conductors between the top electrode and the bottom electrode is formed from a plurality of plates, each plate comprising: a plurality of holes surrounding blocks of conductive metal in the same plane; each block being completely surrounded by one hole of the plurality of holes, so as to be electrically insulated from the plate; and each block being electrically coupled to the plate above it and the plate below it. 7. The integrated circuit of claim 2, wherein the top electrode comprises a plurality of conductive lines that are electrically coupled by at least one conductive line and wherein the bottom electrode comprises a plurality of conductive lines that are electrically coupled by at least one conductive line. 8. The integrated circuit of claim 7, wherein the bottom electrode is of a same shape as the first stack of conductors, and the top electrode is of a same shape as the second stack of conductors and further, wherein each shape comprises: a first line parallel to the edge of the chip; and a plurality of lines coupled to the first line and perpendicular to the first line, wherein each line in the plurality of lines of the first stack of conductors alternates with each line of the plurality of lines of the second stack of conductors so as to form inter-digitized lines that provide capacitance. 9. The integrated circuit of claim 7, wherein the conductive lines on the electrodes and the stacks of conductors comprise discontinuous line segments. 10. An integrated circuit comprising: a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip; integrated circuitry within the circuit area, wherein no active circuit is disposed within the peripheral area; and a barrier within the peripheral area, the barrier at least partially surrounding the circuit area, wherein the barrier includes a capacitor structure integrated therein, wherein the barrier comprises: a bottom electrode, a top electrode vertically spaced from the bottom electrode, and a plurality of metallization layers lying in planes between the top electrode and the bottom electrode, wherein a first stack of conductors is formed from a first plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the bottom electrode, wherein a second stack of conductors is formed from a second plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the top electrode such that at least a portion of the capacitor structure is formed between the first stack of conductors and the second stack of conductors, wherein a third stack of conductors is formed from a third plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the bottom electrode, and wherein a fourth stack of conductors is formed from a fourth plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to the top electrode. 11. The integrated circuit of claim 10, further comprising a fifth stack of conductors formed from a fifth plurality of conductors each of which is in a different one of the metallization layers and is electrically coupled to one of the top or the bottom electrodes. 12. An integrated circuit comprising: a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip; integrated circuitry within the circuit area, wherein no active circuit is disposed within the peripheral area; a barrier within the peripheral area, the barrier at least partially surrounding the circuit area, wherein the barrier includes a first electrode coupled to the integrated circuitry and a second electrode coupled to the integrated circuitry; and a first voltage supply line within the circuit area and a second voltage supply line within the circuit area, wherein the first electrode is coupled to the integrated circuitry via the first voltage supply line and the second electrode is coupled to the integrated circuitry via the second voltage supply line. 13. The integrated circuit of claim 12, wherein the barrier capacitively couples the first voltage supply line with the second voltage supply line. 14. The integrated circuit of claim 12, wherein at least one of the first electrode and/or the second electrode is electrically coupled to pads on the integrated circuit. 15. The integrated circuit of claim 12, wherein the barrier comprises a double barrier, including a first barrier and a second barrier that is between the first barrier and the circuit area, wherein the second barrier includes a capacitor structure between the first electrode and the second electrode. 16. The integrated circuit of claim 14, wherein the first electrode is electrically coupled to a pad on the integrated circuit and the second electrode is coupled to a supply voltage line. 17. The integrated circuit of claim 15, wherein the first and second barriers comprise a moisture barrier. 18. The integrated circuit of claim 17, further comprising a crackstop surrounding the moisture barrier. 19. An integrated circuit comprising: a substrate including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the substrate; integrated circuitry within the circuit area, wherein no active circuit is disposed within the peripheral area; and a barrier within the peripheral area and surrounding the circuit area, the barrier comprising a first electrode, a second electrode, and means for providing capacitance between the first electrode and the second electrode, wherein the first electrode is electrically coupled to a first voltage supply line which is connected to the integrated circuitry in the circuit area and the second electrode is electrically coupled to a second voltage supply line which is connected to the integrated circuitry in the circuit area. 20. A method of forming an integrated circuit, the method comprising: providing a substrate including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the substrate; forming integrated circuitry within the circuit area wherein no active circuit is disposed within the peripheral area; and forming a barrier within the peripheral area and surrounding the circuit area, the barrier including a capacitor structure therein, wherein forming the barrier comprises: forming a bottom electrode, and forming a plurality of conductive lines on metallization layers above the bottom electrode, wherein the plurality of conductive lines is discontinuous along the barrier surrounding the circuit area. 21. The method of claim 20, wherein forming the barrier further comprises: forming a plurality of vias connecting the metallization layers; forming a top electrode above the plurality of metallization layers and vertically spaced from them; and electrically coupling the electrodes and the metallization layers such that a first stack of conductors is formed from a plurality of conductive lines each of which is in a different one of the metallization layers and is electrically coupled to the bottom electrode, and wherein a second stack of conductors is formed from a plurality of conductive lines each of which is in a different one of the metallization layers and is electrically coupled to the top electrode such that a capacitor is formed between the first stack of conductors and the second stack of conductors. 22. The method of claim 20, wherein forming the integrated circuitry comprises electrically coupling a plurality of transistors through interconnect lines and vias, wherein the barrier is formed simultaneously with the interconnect lines and vias. 23. The method of claim 20, wherein forming the barrier comprises forming a barrier with a vertical plate capacitor integrated therein. 24. The method of claim 20, wherein forming the barrier comprises forming a barrier with a sandwich capacitor integrated therein. 25. A method of forming an integrated circuit, the method comprising: providing a substrate including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the substrate; forming integrated circuitry within the circuit area wherein no active circuit is disposed within the peripheral area; and forming a barrier within the peripheral area and surrounding the circuit area, the barrier including a capacitor structure therein, wherein forming the barrier comprises forming a barrier with a cage integrated therein.
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