초록 ▼

A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle

A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.

대표청구항 ▼

I claim: 1. A motherboard-based tester that locates defects in memory chips without crashing comprising: a test adaptor board, having a test socket for receiving a memory chip under test for testing by the motherboard-based tester, the test adaptor board for electrically connecting the memory chip

I claim: 1. A motherboard-based tester that locates defects in memory chips without crashing comprising: a test adaptor board, having a test socket for receiving a memory chip under test for testing by the motherboard-based tester, the test adaptor board for electrically connecting the memory chip under test inserted into the test socket to a motherboard attached to the test adaptor board, the motherboard using the memory chip under test inserted into the test socket as a middle portion of a main memory of the motherboard; additional memory chips mounted on the test adaptor board, wherein the additional memory chips and the memory chip under test inserted into the test socket together form an emulated memory-module memory; wherein the motherboard is a main board for a computer using memory modules as the main memory; a first module slot on the motherboard, the first module slot connecting to a first memory module socket on a component side of the motherboard and having a first known good memory module inserted; a second module slot connecting to a location of a second memory module socket on the component side of the motherboard and also connecting to the test adaptor board, wherein the memory chip under test inserted into the test socket on the test adaptor board is accessed through the second module slot; a third module slot on the motherboard, the third module slot connecting to a third memory module socket on the component side of the motherboard and having a second known good memory module inserted; a copy of a basic input-output system (BIOS) stored in the second known good memory module; an operating system image stored in the first known good memory module; a test program stored in the first known good memory module, wherein the test program is executed by a processor on the motherboard that causes memory locations in the memory chip under test to be written and read without crashing the motherboard; and a defect location within the memory chip under test identified by the test program executing on the processor, the defect location being reported to a user, whereby the defect location is identified by the test program without crashing the motherboard by the test program that is not loaded into the memory chip under test. 2. The motherboard-based tester of claim 1 wherein the middle portion of the main memory of the motherboard is between memory addresses that access the first known good memory module and the second known good memory module, wherein the memory chip under test is accessed by memory addresses between memory addresses that access the first known good memory module and memory addresses that access the second known good memory module. 3. The motherboard-based tester of claim 2 wherein the BIOS is disabled from performing a memory sizing test during booting; further comprising: a programmable delay generator, mounted to the test adaptor board, for delaying a signal to the memory chip under test in the test socket in response to the test program executing on the motherboard, whereby margin timing testing is supported by the test adaptor board. 4. The motherboard-based tester of claim 2 further comprising: a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) mounted to the test adaptor board, the SPD-EEPROM storing a configuration for the emulated memory-module memory emulated by the test adaptor board, the configuration including a memory size and a speed parameter, wherein the BIOS reads serial-presence-detect memories on the first known good memory module, on the second known good memory module, and the SPD-EEPROM on the test adaptor board to determine a memory configuration; wherein the test adaptor board is configured to be accessed by middle addresses that do not overlap the copy of the BIOS, the operating system image, or the test program. 5. The motherboard-based tester of claim 2 wherein the test adaptor board with the memory chip under test has a memory size that differs from a memory size of the first and second known good memory modules; wherein interleaving of the memory chip under test is prevented by the memory size being different than memory sizes of the first and second known good memory modules. 6. The motherboard-based tester of claim 2 wherein the first memory module socket and the third memory module socket are mounted to the component side of the motherboard, the component side having integrated circuits mounted thereon and expansion sockets mounted thereon for expansion boards; wherein the test adaptor board is mounted to a solder side of the motherboard, the solder side being opposite to the component side. 7. The motherboard-based tester of claim 6 further comprising: an Advanced Memory Buffer (AMB) mounted to the test adaptor board, the AMB for receiving serial packets sent by the motherboard, and for generating parallel address and data signals to the additional memory chips and to the memory chip under test for testing in the test socket, whereby serial packets from the motherboard are de-serialized by the AMB on the test adaptor board. 8. The motherboard-based tester of claim 6 further comprising: an intervening adaptor board fixedly attached to the motherboard by adaptor pins; a first connector mounted to the intervening adaptor board and electrically connected to the adaptor pins by wiring traces on the intervening adaptor board; a second connector mounted to the test adaptor board, for mating with the first connector, wherein the test adaptor board is removable from the motherboard by disconnecting the second connector from the first connector on the intervening adaptor board that is fixedly attached to the motherboard. 9. The motherboard-based tester of claim 2 wherein the motherboard is in a plurality of motherboards, each motherboard having a test adaptor board and a test socket for testing a memory chip under test without crashing; further comprising: a diagnostic system interface, coupled to the plurality of motherboards, for commanding the motherboard to test the memory chip under test inserted into the test socket and for receiving test results from the motherboard, and a robotic arm, responsive to commands from the diagnostic system interface, for inserting memory chips into the test sockets for use as the memory chip under test, whereby the memory chips inserted into the test sockets on the test adaptor boards are tested by motherboards without crashing. 10. The motherboard-based tester of claim 1 wherein the test adaptor board is a module extender card that is inserted into the second memory module socket on the component side of the motherboard. 11. A crash-resistant memory-chip tester comprising: a robotic device that moves memory chips from an input stack of untested memory chips to an output stack of tested memory chips; a host computer for controlling the robotic device; a plurality of test stations for testing memory chips that are loaded and unloaded by the robotic device, each test station comprising: a test adaptor board; a test socket mounted on the test adaptor board, the test socket for receiving a memory chip inserted by the robotic device for use as a memory chip under test; a motherboard for a personal computer, the motherboard executing a test program in response to commands from the host computer, the test program testing the memory chip inserted into the test socket; a first module slot on the motherboard, the first module slot connecting to a first memory module socket on a component side of the motherboard and having a first known good memory module inserted; a second module slot connecting to a location of a removed second memory module socket on the component side of the motherboard and also connecting to the test adaptor board, wherein the memory chip under test inserted into the test socket on the test adaptor board is accessed through the second module slot; a third module slot on the motherboard, the third module slot connecting to a third memory module socket on the component side of the motherboard and having a second known good memory module inserted; a copy of a basic input-output system (BIOS) stored in the second known good memory module; an operating system image stored in the first known good memory module; and wherein the test program is stored in the first known good memory module, wherein the test program executed by the motherboard causes memory locations in the memory chip under test to be written and read without crashing the motherboard, whereby the memory chip under test is tested without crashing the motherboard using the test program that is not loaded into the memory chip under test. 12. The crash-resistant memory-chip tester of claim 11 wherein the test adaptor board further comprises: additional memory chips mounted on the test adaptor board, wherein the additional memory chips and the memory chip under test inserted into the test socket together form an emulated memory-module memory; wherein a middle portion of a main memory of the motherboard is between memory addresses that access the first known good memory module and the second known good memory module, wherein the memory chip under test is accessed by memory addresses between memory addresses that access the first known good memory module and memory addresses that access the second known good memory module. 13. The crash-resistant memory-chip tester of claim 12 wherein the test adaptor board with the memory chip under test has a memory size that differs from a memory size of the first and second known good memory modules; wherein interleaving of the memory chip under test is prevented by the memory size being different than memory sizes of the first and second known good memory modules. 14. The crash-resistant memory-chip tester of claim 12 wherein each test adaptor board further comprises: a second test socket mounted on the test adaptor board, the second test socket for receiving a second memory chip under test inserted by the robotic device, wherein the motherboard tests both the memory chip under test and the second memory chip under test, whereby two memory modules are tested by each motherboard. 15. The crash-resistant memory-chip tester of claim 12 further comprising: an intervening adaptor board fixedly attached to the motherboard by adaptor pins; a first connector mounted to the intervening adaptor board and electrically connected to the adaptor pins by wiring traces on the intervening adaptor board; a second connector mounted to the test adaptor board, for mating with the first connector, whereby the test adaptor board is removable from the motherboard by disconnecting the second connector from the first connector on the intervening adaptor board that is fixedly attached to the motherboard. 16. A reliable multiple-motherboard memory tester comprising: main system means for controlling testing of memory chips on multiple motherboards; a plurality of test station means for testing memory chips, each test station means comprising: test socket means for receiving a memory chip under test for testing; motherboard means, controlled by the main system means, for executing a test program to test a memory chip under test inserted into the test socket means; and test adaptor board means, mounted to the motherboard means, for electrically connecting the test socket means to a memory bus means on the motherboard means; additional memory chips mounted on the test adaptor board means, wherein the additional memory chips and the memory chip under test form an emulated memory-module memory; first module slot means for connecting to a first memory module socket on the motherboard means, and for receiving a first known good memory module inserted; second module slot means for connecting to a location of a second memory module socket on the motherboard means, and for connecting to the test adaptor board means, wherein the memory chip under test inserted into the test socket means on the test adaptor board means is accessed through the second module slot means; third module slot means for connecting to a third memory module socket on the motherboard means, and for receiving a second known good memory module inserted; a copy of a basic input-output system (BIOS) stored in the second known good memory module; an operating system image stored in the first known good memory module; wherein the test program is stored in the first known good memory module, wherein the test program executed by the motherboard means causes memory locations in the memory chip under test to be written and read without crashing the motherboard means, wherein the reliable multiple-motherboard memory tester has a plurality of the motherboard means, each motherboard means having an attached test adaptor board means with a test socket means, each motherboard means for executing the test program on a different memory chip under test in parallel with other motherboard means; whereby the memory chip under test is tested without crashing the motherboard means using the test program that is not loaded into the memory chip under test. 17. The reliable multiple-motherboard memory tester of claim 16 further comprising: Advanced Memory Buffer (AMB) means, mounted to the test adaptor board means, for receiving serial packets sent by the motherboard means, and for generating parallel address and data signals to the additional memory chips and to the memory chip under test for testing in the test socket means; a defect location within the memory chip under test identified by the test program executing on the motherboard means, the defect location being reported to the main system means, whereby the defect location is identified by the test program without crashing the motherboard means by the test program that is not loaded into the memory chip under test. 18. The reliable multiple-motherboard memory tester of claim 16 wherein a middle portion of a main memory of the motherboard means is between memory addresses that access the first known good memory module and the second known good memory module, wherein the memory chip under test is accessed by memory addresses between memory addresses that access the first known good memory module and memory addresses that access the second known good memory module. 19. The reliable multiple-motherboard memory tester of claim 18 further comprising: edge socket means, attached to the test adaptor board means, for connecting the test adaptor board means to an edge of the motherboard means; wherein the test adaptor board means is perpendicular to the motherboard means; wherein the test adaptor board means with the memory chip under test inserted has a memory size that differs from a memory size of the first and second known good memory modules; wherein interleaving of the memory chip under test is prevented by the memory size being different than memory sizes of the first and second known good memory modules. 20. The reliable multiple-motherboard memory tester of claim 16 further comprising: robotic means, controlled by the main system means, for grasping a memory chip and inserting the memory chip into the test socket means, the robotic means also for grasping and removing the memory chip from the test socket means after completion of the test program, and moving the memory chip to an output means for storing tested memory chips when the motherboard means indicates to the main system means that the memory chip has passed the test program, whereby the memory chips are moved by the robotic means.