A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such d
A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.
대표청구항▼
What is claimed is: 1. An apparatus comprising: a task scheduler to retrieve and/or store data objects; a function block to provide a request to the task scheduler, the request associated with a data object from among the data objects retrievable and/or storable by the task scheduler; a first memor
What is claimed is: 1. An apparatus comprising: a task scheduler to retrieve and/or store data objects; a function block to provide a request to the task scheduler, the request associated with a data object from among the data objects retrievable and/or storable by the task scheduler; a first memory to store the request, the request having an identifier field to store an identifier associated with the function block, and the request having a field to store a computation count associated with the function block, the computation count correlated to a number of computations of use of the function block; second memory to store a first table; and a functional unit to read an entry stored in the first table based upon the identifier and the computation count, the computation count used to locate the entry in the first table; wherein the entry indicates a memory address for the data object; wherein the second memory further stores a second table; and the functional unit, in response to reading the identifier, reads an offset address stored in the second table, wherein the functional unit reads the entry stored in the first table based upon the offset address and the computation count. 2. The apparatus as set forth in claim 1, wherein the second memory comprises at least two memory devices. 3. The apparatus as set forth in claim 1, wherein the second memory is logically partitioned into at least a first memory block and a second memory block, wherein the first table is stored in the first memory block and the second table is stored in the second memory block. 4. The apparatus as set forth in claim 1, wherein the request is a download request so that the functional unit causes a memory read of the data object according to the memory address. 5. The apparatus as set forth in claim 1, wherein the request is an upload request so that the functional unit causes a memory write of the data object according to the memory address. 6. The apparatus as set forth in claim 1, the function block comprising a register to store the identifier. 7. The apparatus as set forth in claim 1, the function block comprising a register to store a computation round number. 8. The apparatus as set forth in claim 7, wherein the computation round number is updated when the function block completes an operation on the data object. 9. The apparatus as set forth in claim 8, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time. 10. The apparatus as set forth in claim 1, wherein the computation count is updated when the function block completes an operation on the data object. 11. The apparatus as set forth in claim 1, wherein the computation count is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time. 12. The apparatus as set forth in claim 1, wherein the data object is indicative of a discrete multi-tone (DMT) symbol. 13. The apparatus as set forth in claim 12, wherein the computation round number is updated when the function block completes an operation on the data object. 14. The apparatus as set forth in claim 13, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time. 15. The apparatus as set forth in claim 12, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time. 16. The apparatus as set forth in claim 1, the first memory comprising a queue. 17. The apparatus as set forth in claim 1, comprising a memory device, the memory device comprising the first memory and the second memory. 18. An apparatus comprising: an arrangement of components to process at least one channel symbol, corresponding to a communication channel, during a first channel symbol time, the arrangement including: a memory in which to store data objects associated with channel symbols; a task scheduler to retrieve and/or store the data objects; a function block to provide a request to the task scheduler for a data object, the requested data object being associated with a channel symbol, the request comprising an identifier to identify the function block and the request comprising a computation count, the computation count correlated to a number of computations of use of the function block, wherein the computation count is updated in response to the function block performing an operation on the data object; and a functional unit to use the identifier and the computation count to provide a memory address for the data object, the computation count used to locate an entry in a table to provide the memory address; wherein the computation count is re-set to a pre-assigned number for a second channel symbol time subsequent to the first channel symbol time.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (97)
So, Woon Seob; Yang, Sung Mo; Kim, Jin Tae, ADSL subscriber processing equipment in ATM switch.
John C. Sinibaldi ; Himanshu Parikh ; Veerbhadra S. Kulkarni ; David A. Frye ; Gary L. Turbeville, Adaptive method and apparatus for allocation of DSP resources in a communication system.
Green Douglas E. ; Jones Kenneth D. ; Peralta Rick ; Voellmann Frank O. ; Osler Bruce ; Grummer Grant, Apparatus and method for processing multiple telephone calls.
Daryl Carvis Cromer ; Brandon John Ellison ; Eric Richard Kern ; Howard Jeffrey Locker ; James Peter Ward, Automatic reconfiguration system for change in management servers having protocol destination addresses.
Tang Jun ; So John Ling Wing, Computer operating process allocating tasks between first and second processors at run time based upon current processor load.
Gulick Dale ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having a dedicated multimedia engine including multimedia memory.
Bobak Roman A. ; Compton Scott Brady ; Johnson Jon K. ; Martens Alan F. ; Maurer Max M. ; Meck David Lee ; Richardson William R. ; Wright Michael Allen, Cross-system data piping using an external shared memory.
Sollars Donald L., Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations.
Chien-Meen Hwang ; Hungming Chang ; Maged F. Barsoum ; Muoi V. Huynh ; Eugen Gershon ; Fred Berkowitz ; Bin Guo, Differential encoding arrangement for a discrete multi-tone transmission system.
Hasegawa,Kazutomo; Miyoshi,Seiji; Awata,Yutaka; Sasaki,Takashi; Koizumi,Nobukazu, Digital subscriber line communicating system and a transceiver in the system.
Divine James ; Niehaus Jeffrey ; Dokic Miroslav ; Rao Raghunath ; Ritchie Terry ; Scott ; III Baker ; Pacourek John ; Luo Zheng, Dual processor digital audio decoder with shared memory data transfer and task partitioning for decompressing compressed audio data, and systems and methods using the same.
Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Noel, Jr., Francis Edward; Rincon, Ann Marie; Strole, Norman Clark, Field programmable network processor and method for customizing a network processor.
Gant Alan D. (Garland TX) Nobles David A. (Garland TX) Jones Thomas M. (Dallas TX) Kimmel Arthur T. (Dallas TX), Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a comput.
Lyon Thomas ; Newman Peter ; Minshall Greg ; Hinden Robert ; Liaw Fong Ching ; Hoffman Eric ; Huston Lawrence B. ; Roberson William A., Method and apparatus for dynamically shifting between routing and switching packets in a transmission network.
Kao Chiihsin ; Chen Chunta ; Liu Ming-Kang, Method of configuring and dynamically adapting data and energy parameters in a multi-channel communications system.
Pechanek Gerald G. ; Revilla Juan Guillermo ; Barry Edwin F., Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
Pechanek Gerald G. ; Drabenstott Thomas L. ; Revilla Juan Guillermo ; Strube David Carl ; Morris Grayson, Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication.
Barry Edwin F. ; Pechanek Gerald G. ; Drabenstott Thomas L. ; Wolff Edward A. ; Pitsianis Nikos P. ; Morris Grayson, Methods and apparatus for manarray PE-PE switch control.
Pechanek Gerald G. ; Barry Edwin F. ; Revilla Juan Guillermo ; Larsen Larry D., Methods and apparatus for scalable instruction set architecture with dynamic compact instructions.
Mikael Isaksson SE; Magnus Johansson SE; Harry Tonvall SE; Lennart Olsson SE; Tomas Stefansson SE; Hans Ohman SE; Gunnar Bahlenberg SE; Anders Isaksson SE; Goran Okvist SE; Lis-Marie Ljunggr, Multi-carrier transmission systems.
Parruck, Bidyut; Nguyen, Joseph A.; Ramakrishnan, Chulanur, PROCESSOR-BASED ARCHITECTURE FOR FACILITATING INTEGRATED DATA TRANSFER BETWEEN BOTH ATM AND PACKET TRAFFIC WITH A PACKET BUS OR PACKET LINK, INCLUDING BIDIRECTIONAL ATM-TO-PACKET FUNCTIONALLY FOR ATM.
Liu Young Way ; Liu Ming-Kang ; Chen Steve ; Gross John Nicholas, Program for controlling DMT based modem using sub-channel selection to achieve scaleable data rate based on available signal processing resources.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Chiu, Manfred F.; Hill, Gregory C.; Buckley, Clifford James; Holten, Jens Arne; Eich, Steven A.; Grimes, Michael E.; Sudhakar, Yerrapalli R.; Peck, Anthony Peter, SVC signaling system and method.
Baker Robert G. (Delray Beach FL) Eduartez Jose A. (Miami Beach FL) Huynh Duy Q. (Boca Raton FL) Swingle Paul R. (Delray Beach FL) Yong Suksoon (Boca Raton FL), System and method for efficiently loading and removing selected functions on digital signal processors without interrupt.
Robinson Jeffrey I. (New Fairfield CT) Rouse Keith (New Milford CT) Krassowski Andrew J. (San Jose CA) Montlick Terry F. (Bethlehem CT), System for dividing processing tasks into signal processor and decision-making microprocessor interfacing therewith.
Guezou Jean Adrien,FRX ; Ollivier Marcel,FRX ; Paris Bernard,FRX, System for interchanging data between data processor units having processors interconnected by a common bus.
Czerwiec Richard M. ; Sutherland Joseph E. ; Schepers Peter M. L.,BEX ; Van Wonterghem Geert A. E.,BEX ; Simmering Marlin V. ; Boeykens Eduard C. M.,BEX ; Van Der Auwera Chris,BEX ; Van Rompu Peter A, Telecommunications system for providing both narrowband and broadband services to subscribers.
Hoff James ; Brown Randall L. ; Perry Thomas J. ; Mualim Satrio P. ; Plyler Kevin B. ; Spenik John W. ; Southway James B. ; Sciabica Frank ; Baer Scott J., Wide area network system providing secure transmission.
Liu Young Way ; Liu Ming-Kang ; Chen Steve, xDSL DMT modem using sub-channel selection to achieve scaleable data rate based on available signal processing resources.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.