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Method of producing an electronic component with flexible bonding 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
  • H01L-021/50
  • H01L-021/31
  • H01L-021/469
출원번호 UP-0124515 (2005-05-06)
등록번호 US-7820482 (2010-11-15)
우선권정보 DE-199 27 750(1999-06-17)
발명자 / 주소
  • Hedler, Harry
  • Haimerl, Alfred
출원인 / 주소
  • Qimonda AG
대리인 / 주소
    Edell, Shapiro & Finnan, LLC
인용정보 피인용 횟수 : 0  인용 특허 : 43

초록

A method for producing an electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the

대표청구항

We claim: 1. A method of producing an electronic component, the method comprising: providing an electronic component including: an electronic circuit with a first surface; and electrical contacts at least on the first surface for electrical bonding of the electronic circuit; applying at least one e

이 특허에 인용된 특허 (43)

  1. Kawakita Tetsuo (Takatsuki JPX) Hatada Kenzo (Katano JPX), Bump electrode for connecting electronic components.
  2. Matsuda Tatsuharu (Kawasaki JPX) Minamizawa Masaharu (Kawasaki JPX), Bump electrode, semiconductor integrated circuit device using the same, multi-chip module having the semiconductor integ.
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  7. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
  8. Naundorf Gerhard,DEX ; Wissbrock Horst,DEX, Conductor track structures arranged on a nonconductive support material, especially fine conductor track structures, and method for producing the same.
  9. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  10. Jimarez Miguel Angel ; Milkovich Cynthia Susan ; Pierson Mark Vincent, Flip chip C4 extension structure and process.
  11. Kulesza Frank W. (Winchester MA) Estes Richard H. (Pelham NH), Flip chip bonding method using electrically conductive polymer bumps.
  12. McMahon John F., Flip-chip having electrical contact pads on the backside of the chip.
  13. Karnezos Marcos (Palo Alto CA), Interconnect structure for PC boards and integrated circuits.
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  15. Saiki Atsushi (Musashimurayama JA) Sato Kikuji (Kokubunji JA) Harada Seiki (Hachioji JA) Tsunoda Terue (Tokyo JA) Oba Yoichi (Hachioji JA), Isolating protective film for semiconductor devices and method for making the same.
  16. Reetz Manfred T.,DEX ; Winter Martin,DEX ; Dumpich Gunter,DEX ; Lohau Jens,DEX, Lithographical process for production of nanostructures on surfaces.
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  19. Kragl Hans (Ober-Ramstadt DEX) Rech Wolf-Henning (Griesheim DEX), Method for producing a hybrid integrated optical circuit and device for emitting light waves.
  20. Yamazaki, Shunpei, Method of fabricating a MIS transistor.
  21. Fjelstad Joseph, Method of making compliant microelectronic assemblies.
  22. Nelson Gregory H. (Gilbert AZ), Method of manufacturing an interconnect device having coplanar contact bumps.
  23. Smith John W., Methods of making microelectronic corrections with liquid conductive elements.
  24. Distefano Thomas H. (Monte Sereno CA) Kovac Zlata (Los Gatos CA) Grange John (Cupertino CA), Microelectronic bonding with lead motion.
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  29. Michael Ball, Recessed tape and method for forming a BGA assembly.
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  36. Nishimura Hiroyuki (Hyogo JPX) Adachi Hiroshi (Hyogo JPX) Adachi Etsushi (Hyogo JPX) Yamamoto Shigeyuki (Hyogo JPX) Minami Shintaro (Hyogo JPX) Harada Shigeru (Hyogo JPX) Tajima Toru (Hyogo JPX) Hagi, Semiconductor device having a multilayer interconnection structure.
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  38. Mukai Kiichiro (Hachioji JPX) Harada Seiki (Hachioji JPX) Muramatsu Shin-ichi (Hachioji JPX) Hiraiwa Atsushi (Kokubunji JPX) Takahashi Shigeru (Hachioji JPX) Usami Katsuhisa (Hinodemachi JPX) Iwata S, Semiconductor device with high density low temperature deposited SiwNxHyO.
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  41. Palagonia Anthony Michael, Wafer with elevated contact structures.
  42. Palagonia Anthony Michael, Wafer with elevated contact substructures.
  43. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Wafer-scale techniques for fabrication of semiconductor chip assemblies.

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