초록 ▼

Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform d

Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

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What is claimed is: 1. A turbo decoder for performing parallel decoding of a turbo coded signal that has been generated using almost regular permutation (ARP) interleaving, the turbo decoder comprising: a plurality of turbo decoders including any integer number of turbo decoders between 2 and an in

What is claimed is: 1. A turbo decoder for performing parallel decoding of a turbo coded signal that has been generated using almost regular permutation (ARP) interleaving, the turbo decoder comprising: a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and a plurality of memories; and wherein: during a first decoding cycle: each turbo decoder of the plurality of turbo decoders retrieving information from a first respective, corresponding memory of the plurality of memories as directed by a first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its first respective, corresponding memory thereby generating respective updated information; during a second decoding cycle: each turbo decoder of a first subset of the plurality of turbo decoders retrieving information from a second respective, corresponding memory of the plurality of memories as directed by a second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of a second subset of the plurality of turbo decoders performing a dummy decoding cycle; and the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal. 2. The turbo decoder of claim 1, further comprising: a processing module for performing contention-free memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein: the processing module providing the first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and the processing module providing the second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories. 3. The turbo decoder of claim 1, wherein: the first decoding cycle contention-free mapping being defined according to a first ARP dithering cycle, a first virtual block length, and a first window size; and the second decoding cycle contention-free mapping being defined according to a second ARP dithering cycle, a second virtual block length, and a second window size. 4. The turbo decoder of claim 1, wherein: when performing turbo decoding, a turbo decoder of the plurality of turbo decoders performing almost regular permutation (ARP) interleaving on calculated extrinsic information thereby generating “a priori probability” (app) information. 5. The turbo decoder of claim 1, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; and a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 6. The turbo decoder of claim 1, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing almost regular permutation (ARP) interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing ARP de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 7. The turbo decoder of claim 1, wherein: each turbo decoder of the second subset of the plurality of turbo decoders performing a plurality of dummy decoding cycles; and a number of dummy decoding cycles within the plurality of dummy decoding cycles being a function of an information block within the turbo coded signal. 8. The turbo decoder of claim 1, wherein: the plurality of turbo decoders including a first number of turbo decoders; and the plurality of memories including a second number of memories. 9. The turbo decoder of claim 1, wherein: the turbo decoder being implemented within a wireless personal communication device. 10. The turbo decoder of claim 1, wherein: the turbo decode being implemented within a communication device; and the communication device being implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system. 11. A turbo decoder for performing parallel decoding of a turbo coded signal that has been generated using almost regular permutation (ARP) interleaving, the turbo decoder comprising: a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and a plurality of memories; a processing module for performing contention-free memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein: during a first decoding cycle: each turbo decoder of the plurality of turbo decoders retrieving information from a first respective, corresponding memory of the plurality of memories as directed by a first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories that is provided by the processing module; and each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its first respective, corresponding memory thereby generating updated information; during a second decoding cycle: each turbo decoder of a first subset of the plurality of turbo decoders retrieving information from a second respective, corresponding memory of the plurality of memories as directed by a second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories that is provided by the processing module; and each turbo decoder of a second subset of the plurality of turbo decoders performing a dummy decoding cycle; the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal; and when performing turbo decoding, a turbo decoder of the plurality of turbo decoders performing almost regular permutation (ARP) interleaving on the calculated extrinsic information thereby generating “a priori probability” (app) information. 12. The turbo decoder of claim 11, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; and a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 13. The turbo decoder of claim 11, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing almost regular permutation (ARP) interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing ARP de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 14. The turbo decoder of claim 11, wherein: each turbo decoder of the second subset of the plurality of turbo decoders performing a plurality of dummy decoding cycles; and a number of dummy decoding cycles within the plurality of dummy decoding cycles being a function of an information block within the turbo coded signal. 15. The turbo decoder of claim 11, wherein: the turbo decoder being implemented within a communication device; and the communication device being implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system. 16. A turbo decoder that is operable to perform parallel decoding of a turbo coded signal that has been generated using almost regular permutation (ARP) interleaving, the turbo decoder comprising: a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and a plurality of memories; and wherein: during a first decoding cycle: each turbo decoder of the plurality of turbo decoders retrieving information from a first respective, corresponding memory of the plurality of memories as directed by a first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its first respective, corresponding memory thereby generating respective updated information; during a second decoding cycle: each turbo decoder of a first subset of the plurality of turbo decoders retrieving information from a second respective, corresponding memory of the plurality of memories as directed by a second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of a second subset of the plurality of turbo decoders performing a plurality of dummy decoding cycles; and a number of dummy decoding cycles within the plurality of dummy decoding cycles being a function of an information block within the turbo coded signal; the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal; the first decoding cycle contention-free mapping being defined according to a first ARP dithering cycle, a first virtual block length, and a first window size; the second decoding cycle contention-free mapping being defined according to a second ARP dithering cycle, a second virtual block length, and a second window size; the plurality of turbo decoders including a first number of turbo decoders; and the plurality of memories including a second number of memories. 17. The turbo decoder of claim 16, further comprising: a processing module for performing contention-free memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein: the processing module providing the first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and the processing module providing the second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories. 18. The turbo decoder of claim 16, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; and a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 19. The turbo decoder of claim 16, wherein a turbo decoder of the plurality of turbo decoders includes: a first soft-in/soft-out (SISO) decoder for: receiving a plurality of metrics associated with the turbo coded signal; and performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information; an interleaver module for performing almost regular permutation (ARP) interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information; a de-interleaver module for performing ARP de-interleaving on the second extrinsic information thereby generating second app information; and an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal. 20. The turbo decoder of claim 16, wherein: the turbo decoder being implemented within a communication device; and the communication device being implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.