IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0748327
(2007-05-14)
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등록번호 |
US-7833886
(2011-01-16)
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발명자
/ 주소 |
- Giles, Luis-Felipe
- Goldbach, Matthias
- Bartels, Martin
- Kuepper, Paul
|
출원인 / 주소 |
- Infineon Technologies AG
- Qimonda AG
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
15 인용 특허 :
1 |
초록
▼
A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substra
A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.
대표청구항
▼
What is claimed is: 1. A method of producing an integrated circuit, the method comprising: forming a plurality of micro-cavities in a substrate; creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms; depositing an amorphous layer
What is claimed is: 1. A method of producing an integrated circuit, the method comprising: forming a plurality of micro-cavities in a substrate; creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms; depositing an amorphous layer over the substrate; and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities; wherein a semiconductor element is formed using the doping atoms. 2. The method according to claim 1, wherein forming the plurality of micro-cavities comprises implanting ions into the substrate. 3. The method according to claim 2, wherein implanting ions comprises implanting H2+-, He+-, F+-, Ne+-, Cl+-, or Ar+-ions. 4. The method according to claim 2, wherein implanting ions comprises using an implantation dose of between approximately 1015 cm−2 and 1018 cm−2. 5. The method according to claim 2, wherein implanting ions comprises implanting with an energy between 10 keV and 150 keV. 6. The method according to claim 1, wherein annealing comprises annealing at a temperature lower than 650° C. 7. The method according to claim 1, wherein creating the amorphization comprises amorphizing the substrate down to a depth lower than 500 nm. 8. The method according to claim 1, wherein creating the amorphization of the substrate comprises using amorphization ions. 9. The method according to claim 8, wherein the amorphization ions comprise germanium ions and/or silicon ions. 10. The method according to claim 1, wherein the micro-cavities are near an interface between a crystalline region of the substrate and an amorphous region of the substrate formed by the amorphization of the substrate. 11. The method according to claim 1, wherein creating the amorphization of the substrate to form a doping of the substrate comprises implanting one or more of boron atoms, phosphorus atoms, or arsenic atoms into the substrate. 12. The method according to claim 11, wherein implanting comprises introducing boron ions into the substrate or introducing boron fluoride ions into the substrate or introducing boron clusters into the substrate. 13. The method according to claim 1, wherein at least one region, within which region the doping atoms are implanted into the substrate, forms a shallow junction of the semiconductor element. 14. The method according to claim 13, wherein the semiconductor element comprises a transistor. 15. The method according to claim 14, wherein the semiconductor element comprises a field effect transistor. 16. The method according to claim 15, wherein the at least one region, within which region the doping atoms are implanted into the substrate, forms a source region or a drain region of the field effect transistor. 17. The method according to claim 16, wherein a first region, within which the doping atoms are implanted into the substrate, forms a source region of the field effect transistor; and wherein a second region, within which the doping atoms are implanted into the substrate, forms a drain region of the field effect transistor. 18. The method according to claim 1, wherein the substrate comprises a silicon substrate. 19. The method according to claim 18, wherein the substrate is a (100) silicon substrate or a (111) silicon substrate. 20. The method according to claim 1, wherein depositing an amorphous layer comprises depositing at a temperature lower than 500° C. 21. The method according to claim 1, wherein depositing an amorphous layer comprises depositing silicon. 22. The method according to claim 1, wherein depositing an amorphous layer comprises depositing the amorphous layer to a thickness between 5 nm and 100 nm. 23. The method according to claim 1, further comprising performing a TEOS and a nitride spacer deposition after the annealing. 24. The method according to claim 1, wherein creating an amorphization comprises forming a buried crystallographic defect layer near a region of the plurality of micro-cavities. 25. A method of producing an integrated circuit, the method comprising: forming a plurality of micro-cavities in a substrate; creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms; and depositing an amorphous layer over the substrate; annealing the substrate at a temperature lower than 600° C., such that at least a part of the crystallographic defects is eliminated using the micro-cavities; wherein a semiconductor element is formed using the doping atoms. 26. The method according to claim 25, wherein forming the plurality of micro-cavities comprises implanting ions into the substrate. 27. The method according to claim 25, wherein creating the amorphization of the substrate is performed such that the substrate is amorphized down to a depth lower than 500 nm. 28. The method according to claim 25, wherein creating the amorphization of the substrate comprises using amorphization ions. 29. The method according to claim 28, wherein the amorphization ions comprise germanium ions and/or silicon ions. 30. The method according to claim 25, wherein creating the amorphization of the substrate to form the doping of the substrate comprises implanting one of boron atoms, phosphorous atoms, or arsenic atoms into the substrate. 31. The method according to claim 25, wherein the implanting comprises introducing boron ions into the substrate or introducing boron fluoride ions into the substrate or introducing boron clusters into the substrate. 32. The method according to claim 25, wherein at least one region, within which region the doping atoms are implanted into the substrate, forms a shallow junction of the semiconductor element. 33. The method according to claim 25, wherein the semiconductor element comprises a transistor. 34. The method according to claim 33, wherein the semiconductor element comprises a field effect transistor. 35. The method according to claim 34, wherein at least one region, within which region the doping atoms are implanted into the substrate, forms a source region or a drain region of the field effect transistor. 36. The method according to claim 35, wherein a first region, within which the doping atoms are implanted into the substrate, forms a source region of the field effect transistor; and wherein a second region, within which the doping atoms are implanted into the substrate, forms a drain region of the field effect transistor. 37. The method according to claim 25, wherein the substrate is a silicon substrate. 38. The method according to claim 25, further comprising depositing a TEOS and a nitride spacer after the annealing. 39. The method according to claim 25, wherein the amorphization is performed such that a buried crystallographic defect layer near a region of the plurality of micro-cavities is formed. 40. The method according to claim 1, wherein depositing an amorphous layer on top of the substrate is performed after creating the amorphization to form crystallographic defects and the doping of the substrate with doping atoms. 41. The method according to claim 1, wherein depositing of an amorphous layer on top of the substrate is performed at a surface of the substrate being used for creating the amorphization of the substrate and the doping of the substrate with doping atoms. 42. The method according to claim 25, wherein annealing the substrate is performed at a temperature lower than 580° C. 43. The method according to claim 25, wherein after creating an amorphization and a doping of the substrate with doping atoms, a rapid thermal process (RTP), a laser annealing or a flash annealing of the substrate to produce the semiconductor element is performed. 44. The method according to claim 25, wherein the annealing is a solid-phase epitaxial regrowth (SPER) which is performed to eliminate at least a part of the crystallographic defects by means of the micro-cavities.
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