IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0938236
(2007-11-09)
|
등록번호 |
US-7841820
(2011-01-31)
|
발명자
/ 주소 |
- Bonora, Anthony C.
- Gould, Richard H.
- Hine, Roger G.
- Krolak, Michael
- Speasl, Jerry A.
|
출원인 / 주소 |
- Crossing Automation, Inc.
|
대리인 / 주소 |
Martine Penilla & Gencarella, LLP
|
인용정보 |
피인용 횟수 :
24 인용 특허 :
13 |
초록
▼
The present invention is a wafer transfer system that transports individual wafers between chambers within an isolated environment. In one embodiment, a wafer is transported by a wafer shuttle that travel within a transport enclosure. The interior of the transport enclosure is isolated from the atmo
The present invention is a wafer transfer system that transports individual wafers between chambers within an isolated environment. In one embodiment, a wafer is transported by a wafer shuttle that travel within a transport enclosure. The interior of the transport enclosure is isolated from the atmospheric conditions of the surrounding wafer fabrication facility. Thus, an individual wafer may be transported throughout the wafer fabrication facility without having to maintain a clean room environment for the entire facility. The wafer shuttle may be propelled by various technologies, such as, but not limited to, magnetic levitation or air bearings. The wafer shuttle may also transport more than one wafer simultaneously. The interior of the transport enclosure may also be under vacuum, gas-filled, or subject to filtered air.
대표청구항
▼
The invention claimed is: 1. A wafer transport system for moving semiconductor wafers to and from wafer processing chambers, comprising: a wafer carrier configured to travel along a path; a first wafer transfer chamber interfaced with a first wafer processing chamber, the first wafer transfer chamb
The invention claimed is: 1. A wafer transport system for moving semiconductor wafers to and from wafer processing chambers, comprising: a wafer carrier configured to travel along a path; a first wafer transfer chamber interfaced with a first wafer processing chamber, the first wafer transfer chamber disposed in the path of the wafer carrier, the first wafer transfer chamber having a first wafer transfer mechanism defined to transfer the semiconductor wafer to and from the first wafer processing chamber that is not disposed in the path but is adjacent to the path; a second wafer transfer chamber interfaced with a second wafer processing chamber, the second wafer transfer chamber disposed in the path of the wafer carrier, the second wafer transfer chamber having a second wafer transfer mechanism defined to enable a transfer of the semiconductor wafer to and from the second wafer processing chamber that is not disposed in the path but is adjacent to the path; and a wafer transfer enclosure disposed in the path to connect the first wafer transfer chamber with the second wafer transfer chamber, wherein each of the first wafer transfer chamber, the second wafer transfer chamber and the wafer transfer enclosure have path segments that couple together to define the path on which the wafer carrier moves in and along the wafer transfer enclosure, the first wafer transfer chamber and the second wafer transfer chamber; wherein each of the first and second wafer transfer chambers and the wafer transfer enclosure is configured to support two wafer carriers in a vertically stacked orientation, so as to facilitate independent movement of each of the two wafer carriers through each of the first and second wafer transfer chambers and the wafer transfer enclosure in an in-line fashion. 2. The wafer transport system as recited in claim 1, wherein the first wafer transfer chamber and the first wafer processing chamber are defined to be connected through a first transition chamber, the first transition chamber being defined to provide an environmental isolation between the first wafer transfer chamber and the first wafer processing chamber. 3. The wafer transport system as recited in claim 1, wherein one or both of the first and second wafer transfer chambers having a plurality of openings each defined to receive one of a plurality of wafer processing chambers. 4. The wafer transport system as recited in claim 1, wherein one or both of the first and second wafer transfer mechanisms includes a robot mechanism to grab the semiconductor wafer from the wafer carrier in the path and transfer the semiconductor wafer from the path to the first or second wafer processing chamber, respectively. 5. The wafer transport system as recited in claim 1, wherein one or both of the first and second wafer transfer mechanisms is defined on a top side wall of the first or second wafer transfer chamber, respectively. 6. The wafer transport system as recited in claim 1, wherein one or both of the first and second wafer transfer mechanisms is defined on a bottom side wall of the first or second wafer transfer chamber, respectively. 7. The wafer transport system as recited in claim 1, wherein the path is magnetic and at least one of the two wafer carriers is defined to float on the path. 8. The wafer transport system as recited in claim 1, further including a propulsion coil defined to control the movement of at least one of the two wafer carriers. 9. A wafer transport system for moving semiconductor wafers to and from wafer processing chambers, comprising: a first wafer transport tube, the first wafer transport tube defining a path along which a wafer carrier is configured to travel; a first wafer transfer chamber coupled to the first wafer transport tube in an in-line configuration, the first wafer transfer chamber facilitating movement of the wafer carrier in-line with the path defined by the first wafer transport tube; a first wafer processing chamber coupled to the first wafer transfer chamber; wherein the first wafer transfer chamber includes a first wafer transfer mechanism for transferring a semiconductor wafer to and from the first wafer processing chamber; wherein each of the first wafer transport tube and the first wafer transfer chamber is configured to support two wafer carriers in a vertically stacked orientation, so as to facilitate independent movement of each of the two wafer carriers through both the first wafer transport tube and the first wafer transfer chamber in an in-line fashion. 10. The wafer transport system of claim 9, further including a second wafer transfer chamber coupled to the first wafer transport tube in an in-line configuration at an end of the first wafer transport tube opposite that of the first wafer transfer chamber, the second wafer transfer chamber facilitating movement of the wafer carrier in-line with the path defined by the first wafer transport tube; and a second wafer processing chamber coupled to the second wafer transfer chamber; wherein the second wafer transfer chamber includes a second wafer transfer mechanism for transferring a semiconductor wafer to and from the second wafer processing chamber. 11. The wafer transport system of claim 9, further including a second wafer transport tube coupled to the first wafer transfer chamber in an in-line configuration at an end of the first wafer transfer chamber opposite the first wafer transport tube, the second wafer transport tube facilitating movement of the wafer carrier in-line with the path defined by the first wafer transport tube. 12. The wafer transport system of claim 9, wherein the first wafer transfer chamber and the first wafer processing chamber are defined to be connected through a transition chamber, the transition chamber being defined to provide an environmental isolation between the first wafer transfer chamber and the first wafer processing chamber. 13. The wafer transport system as recited in claim 9, wherein the first wafer transfer chamber having a plurality of openings each defined to receive one of a plurality of wafer processing chambers. 14. The wafer transport system as recited in claim 9, wherein the first wafer transfer mechanism includes a robot mechanism to grab the semiconductor wafer from the wafer carrier and transfer the semiconductor wafer to the first wafer processing chamber. 15. The wafer transport system as recited in claim 9, wherein the first wafer transfer mechanism is defined on a top side wall of the first wafer transfer chamber. 16. The wafer transport system as recited in claim 9, wherein the wafer transfer mechanism is defined on a bottom side wall of the first wafer transfer chamber. 17. The wafer transport system as recited in claim 9, wherein each of the first wafer transport tube and the first wafer transfer chamber includes a magnetic levitation system configured to propel the wafer carrier through both the first wafer transport tube and the first wafer transfer chamber in an in-line fashion.
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