$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Epitaxial deposition of doped semiconductor materials 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0644673 (2006-12-22)
등록번호 US7863163 (2010-12-20)
발명자 / 주소
  • Bauer, Matthias
출원인 / 주소
  • ASM America, Inc.
대리인 / 주소
    Knobbe Martens Olson & Bear LLP
인용정보 피인용 횟수 : 100  인용 특허 : 83

초록 ▼

A method for depositing a carbon doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 700 torr in a process chamber housing a patterned substrate having exposed single crystal material. The method further comprises providing a flow of a silicon source gas to the

대표청구항 ▼

I claim: 1. A method for depositing a carbon doped epitaxial semiconductor layer, the method comprising:maintaining a pressure of greater than about 700 torr in a process chamber housing a patterned substrate having exposed single crystal material and at least a second different exposed material;pro

이 특허에 인용된 특허 (83)

  1. Bohling David A. (Emmaus PA) Muhr Gregory T. (Allentown PA) Bassner Sherri L. (Lansdale PA), Amino replacements for arsine, antimony and phosphine.
    상세보기
  2. Conger Darrell R. (Portland OR) Posa John G. (Lake Oswego OR) Wickenden Dennis K. (Lake Oswego OR), Apparatus for depositing material on a substrate.
    상세보기
  3. Gates Stephen McConnell ; Neumayer Deborah Ann, Atomic layer deposition with nitrate containing precursors.
    상세보기
  4. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.
    상세보기
  5. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.
    상세보기
  6. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.
    상세보기
  7. Murthy,Anand; Glass,Glenn A.; Westmeyer,Andrew N.; Hattendorf,Michael L.; Wank,Jeffrey R., CMOS transistor junction regions formed by a CVD etching and deposition sequence.
    상세보기
  8. Todd, Michael A., CVD syntheses of silicon nitride materials.
    상세보기
  9. Sang-Gi Ko KR, Capacitor and method of fabricating the same.
    상세보기
  10. Whitmarsh Christopher K. (Schenectady NY) Interrante Leonard V. (Schenectady NY), Carbosilane polymer precursors to silicon carbide ceramics.
    상세보기
  11. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
    상세보기
  12. Dickson Charles R. (Trenton NJ), Deposition feedstock and dopant materials useful in the fabrication of hydrogenated amorphous silicon alloys for photovo.
    상세보기
  13. Todd,Michael A., Deposition of amorphous silicon-containing films.
    상세보기
  14. Todd, Michael A., Deposition over mixed substrates.
    상세보기
  15. Takasu Katsuji,JPX ; Tsuda Hisanori,JPX ; Sano Masafumi,JPX ; Hirai Yutaka,JPX, Device for forming deposited film.
    상세보기
  16. Roger Leung ; Denis Endisch ; Songyuan Xie ; Nigel Hacker ; Yanpei Deng, Dielectric films for narrow gap-fill applications.
    상세보기
  17. Todd, Michael A., Dopant precursors and ion implantation processes.
    상세보기
  18. Lee Ellis,TWX, Dual damascene structure and its manufacturing method.
    상세보기
  19. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with composite atomic barrier film and process for making same.
    상세보기
  20. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with rubidium barrier film and process for making same.
    상세보기
  21. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with strontium barrier film and process for making same.
    상세보기
  22. Brabant,Paul D.; Italiano,Joseph P.; Arena,Chantal J.; Tomasini,Pierre; Raaijmakers,Ivo; Bauer,Matthias, Epitaxial semiconductor deposition methods and structures.
    상세보기
  23. Wang Chein-Cheng,TWX ; Chang Shih-Chanh,TWX, Fabricating method of glue layer and barrier layer.
    상세보기
  24. Michael A. Todd, Fluorine-containing materials and processes.
    상세보기
  25. Fitzgerald, Eugene A.; Hammond, Richard; Currie, Matthew, Gate technology for strained surface channel and strained buried channel MOSFET devices.
    상세보기
  26. Li Yaun-Min ; Bennett Murray S. ; Yang Liyou, Increasing stabilized performance of amorphous silicon based devices produced by highly hydrogen diluted lower temperatu.
    상세보기
  27. Changming Jin ; Kelly J. Taylor ; Wei William Lee, Integrated circuit dielectric and method.
    상세보기
  28. Hoinkis Mark D., Integrated circuits with copper metallization for interconnections.
    상세보기
  29. Pomarede,Christophe F.; Givens,Michael E.; Shero,Eric J.; Todd,Michael A., Integration of high k gate dielectric.
    상세보기
  30. Naoki Komai JP; Shingo Kadomura JP; Mitsuru Taguchi JP; Akira Yoshio JP; Takaaki Miyamoto JP, Interconnection structure and fabrication process therefor.
    상세보기
  31. Huang Richard J. (Milpitas CA) Cheung Robin W. (Cupertino CA) Rakkhit Rajat (Milpitas CA) Lee Raymond T. (Sunnyvale CA), Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC applica.
    상세보기
  32. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
    상세보기
  33. Urabe Koji,JPX, Manufacturing method for contact hole.
    상세보기
  34. Lindert,Nick; Brask,Justin K.; Westmeyer,Andrew, Metal gate transistors with epitaxial source and drain regions.
    상세보기
  35. Iacoponi John A. ; Paton Eric N., Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient.
    상세보기
  36. Posa John G. (Lake Oswego OR), Method and apparatus for producing a constant flow, constant pressure chemical vapor deposition.
    상세보기
  37. Suntola Tuomo,FIX ; Lindfors Sven,FIX ; Soininen Pekka,FIX, Method and equipment for growing thin films.
    상세보기
  38. Alessandra Satta BE; Karen Maex BE; Kai-Erik Elers FI; Ville Antero Saanila FI; Pekka Juha Soininen FI; Suvi P. Haukka FI, Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
    상세보기
  39. Kelly Michael A. (121 Erica Way Portola Valley CA 94028), Method for chemical vapor deposition under a single reactor vessel divided into separate reaction chambers each with its.
    상세보기
  40. Tien-I Bao TW; Syun-Ming Jang TW, Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer.
    상세보기
  41. Kim Yeong-kwan,KRX ; Lee Sang-in,KRX ; Park Chang-soo,KRX ; Kim Young-sun,KRX, Method for forming dielectric film of capacitor having different thicknesses partly.
    상세보기
  42. Logsdon James H. (Kokomo IN) Staller Steven E. (Kokomo IN) De Roo David W. (Carmel IN) Neudeck Gerold W. (West Lafayette IN), Method for forming thin silicon membrane or beam.
    상세보기
  43. Kim Yeong-kwan,KRX ; Lee Sang-in,KRX ; Park Chang-soo,KRX ; Lee Sang-min,KRX, Method for manufacturing thin film using atomic layer deposition.
    상세보기
  44. Suntola Tuomo S. (Espoo FIX) Pakkala Arto J. (Espoo FIX) Lindfors Sven G. (Espoo FIX), Method for performing growth of compound thin films.
    상세보기
  45. Suntola Tuomo (Riihikallio 02610 Espoo 61 SF) Antson Jorma (Urheilutie 22 ; 01350 Vantaa 35 SF), Method for producing compound thin films.
    상세보기
  46. Schafer Herbert,DEX ; Franosch Martin,DEX ; Stengl Reinhard,DEX ; Reisinger Hans,DEX ; Ilg Matthias, Method for the fabrication of a doped silicon layer.
    상세보기
  47. Kang Sang-Bom,KRX ; Lee Sang-In,KRX, Method of and apparatus for forming a metal interconnection in the contact hole of a semiconductor device.
    상세보기
  48. Comita Paul B. ; Forstner Hali J. L. ; Ranganathan Rekha, Method of cleaning CVD cold-wall chamber and exhaust lines.
    상세보기
  49. Sergey D. Lopatin ; Carl Galewski ; Takeshi T. N. Nogami JP, Method of copper interconnect formation using atomic layer copper deposition.
    상세보기
  50. Jing-Cheng Lin TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process.
    상세보기
  51. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of forming a smooth copper seed layer for a copper damascene structure.
    상세보기
  52. Kang Sang-bom,KRX ; Lim Hyun-seok,KRX ; Chae Yung-sook,KRX ; Jeon In-sang,KRX ; Choi Gil-heyun,KRX, Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor.
    상세보기
  53. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
    상세보기
  54. Raaijmakers, Ivo; Haukka, Suvi P.; Saanila, Ville A.; Soininen, Pekka J.; Elers, Kai-Erik; Granneman, Ernst H. A., Method of making conformal lining layers for damascene metallization.
    상세보기
  55. Woo Seock Cheong KR; Hai Won Kim KR, Method of optimizing process of selective epitaxial growth.
    상세보기
  56. Golecki Ilan (Parsippany NJ), Method of producing stoichiometric, epitaxial, monocrystalline films of silicon carbide at temperatures below 900 degree.
    상세보기
  57. Thakur Randhir P. S. ; Breiner Lyle D., Method to form hemi-spherical grain (HSG) silicon.
    상세보기
  58. Wang Fei ; Lyons Christopher F. ; Nguyen Khanh B. ; Bell Scott A. ; Levinson Harry J. ; Yang Chih Yuh, Method using a thin resist mask for dual damascene stop layer etch.
    상세보기
  59. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
    상세보기
  60. Vincent, Jean Louise; O'Neill, Mark Leonard; Withers, Jr., Howard Paul; Beck, Scott Edward; Vrtis, Raymond Nicholas, Organosilicon precursors for interlayer dielectric films with low dielectric constants.
    상세보기
  61. Varhue Walter J., Plasma enhanced CVD process for rapidly growing semiconductor films.
    상세보기
  62. Cheung David ; Yau Wai-Fan ; Mandal Robert P. ; Jeng Shin-Puu ; Liu Kuo-Wei ; Lu Yung-Cheng ; Barnes Michael ; Willecke Ralf B. ; Moghadam Farhad ; Ishikawa Tetsuya ; Poon Tze Wing, Plasma processes for depositing low dielectric constant films.
    상세보기
  63. Rafferty Kevin ; Rowe Bruce, Plural layered metal repair tape.
    상세보기
  64. Gossmann Hans-Joachim Ludwig ; Rafferty Conor Stefan, Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby.
    상세보기
  65. Todd, Michael A., Process for deposition of semiconductor films.
    상세보기
  66. Todd, Michael A.; Hawkins, Mark, Process for deposition of semiconductor films.
    상세보기
  67. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Process for making a semiconductor device with barrier film formation using a metal halide and products thereof.
    상세보기
  68. Siebert Wolfgang,DEX ; Mayer Erwin-Peter,DEX, Process for the production of an epitaxially coated semiconductor wafer.
    상세보기
  69. Speier John L. (Midland MI), Process for the recovery of hydrogen chloride and monomeric alkoxysilanes from mixtures of chloride-containing silicon c.
    상세보기
  70. Ivo Raaijmakers NL; Pekka T. Soininen FI; Ernst H. A. Granneman NL; Suvi P. Haukka FI, Protective layers prior to alternating layer deposition.
    상세보기
  71. Sneh Ofer, Radical-assisted sequential CVD.
    상세보기
  72. Twu Jih-Churng,TWX ; Jang Syun-Ming,TWX ; Yu Chen-Hua,TWX, Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process.
    상세보기
  73. Miyamoto Takaaki,JPX, Semiconductor device contains refractory metal or metal silicide with less than 1% weight of halogen atom.
    상세보기
  74. Mee-Young Yoon KR; Sang-In Lee KR; Hyun-Seok Lim KR, Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer.
    상세보기
  75. Tsuchimoto Junichi (Hyogo JPX), Semiconductor device with arsenic doped silicon thin film interconnections or electrodes.
    상세보기
  76. Ping Er-Xang ; Thakur Randhir P. S., Semiconductor processing method of providing a doped polysilicon layer.
    상세보기
  77. Murthy, Anand S.; Doyle, Brian S.; Roberds, Brian E., Semiconductor transistor having a backfilled channel material.
    상세보기
  78. Sherman Arthur, Sequential chemical vapor deposition.
    상세보기
  79. Hidetoshi Odaka JP; Yuka Kanamori JP; Hiroshi Ito JP; Hideharu Jyono JP; Hiroshi Iwakiri JP; Fumio Kawakubo JP, Silane-functionalized polyether composition.
    상세보기
  80. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
    상세보기
  81. Todd, Michael A.; Raaijmakers, Ivo, Thin films and method of making them.
    상세보기
  82. Gadgil Prasad N. ; Seidel Thomas E., Vertically-stacked process reactor and cluster tool system for atomic layer deposition.
    상세보기
  83. Izumi Hirohiko (Sagamihara JPX), .
    상세보기

이 특허를 인용한 특허 (100)

  1. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
    상세보기
  2. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
    상세보기
  3. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
    상세보기
  4. Lee, Sang-Soo; Ahn, Heetae; Kuo, Augustine, Analog circuits having improved insulated gate transistors, and methods therefor.
    상세보기
  5. Shifren, Lucian; Thompson, Scott E.; Gregory, Paul E., Analog transistor.
    상세보기
  6. Clark, Lawrence T., Bit interleaved low voltage static random access memory (SRAM) and related methods.
    상세보기
  7. Clark, Lawrence T.; McGregor, Michael S.; Rogenmoser, Robert; Kidd, David A.; Kuo, Augustine, Body bias circuits and methods.
    상세보기
  8. Clark, Lawrence T.; McGregor, Michael S.; Rogenmoser, Robert; Kidd, David A.; Kuo, Augustine, Body bias circuits and methods.
    상세보기
  9. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
    상세보기
  10. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
    상세보기
  11. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
    상세보기
  12. Hoffmann, Thomas; Ranade, Pushkar; Thompson, Scott E., CMOS gate stack structures and processes.
    상세보기
  13. Hoffmann, Thomas; Thompson, Scott E.; Ranade, Pushkar, CMOS gate stack structures and processes.
    상세보기
  14. Thompson, Scott E.; Hoffmann, Thomas; Scudder, Lance; Sridharan, U. C.; Zhao, Dalong; Ranade, Pushkar; Duane, Michael; Gregory, Paul E., CMOS structures and processes based on selective thinning.
    상세보기
  15. Thompson, Scott E.; Hoffmann, Thomas; Scudder, Lance; Sridharan, Urupattur C.; Zhao, Dalong; Ranade, Pushkar; Duane, Michael; Gregory, Paul, CMOS structures and processes based on selective thinning.
    상세보기
  16. Clark, Lawrence T.; McWilliams, Bruce; Rogenmoser, Robert, Circuit devices and methods having adjustable transistor body bias.
    상세보기
  17. Lee, Sang-Soo; Boling, Edward J.; Kuo, Augustine; Rogenmoser, Robert, Circuits and devices for generating bi-directional body bias voltages, and methods therefor.
    상세보기
  18. Clark, Lawrence T; Roy, Richard S, Circuits and methods for measuring circuit elements in an integrated circuit device.
    상세보기
  19. Hoffmann, Thomas; Shifren, Lucian; Thompson, Scott E.; Ranade, Pushkar; Wang, Jing; Gregory, Paul E.; Sonkusale, Sachin R.; Scudder, Lance; Zhao, Dalong; Bakhishev, Teymur; Liu, Yujie; Wang, Lingquan; Zhang, Weimin; Pradhan, Sameer; Duane, Michael; Kim, Sung Hwan, Deeply depleted MOS transistors having a screening layer and methods thereof.
    상세보기
  20. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  21. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  22. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  23. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  24. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  25. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
    상세보기
  26. Clark, Lawrence T.; Shifren, Lucian; Roy, Richard S., Dynamic random access memory (DRAM) with low variation transistor peripheral circuits.
    상세보기
  27. Shifren, Lucian; Ranade, Pushkar, Electronic device with controlled threshold voltage.
    상세보기
  28. Shifren, Lucian; Ranade, Pushkar, Electronic device with controlled threshold voltage.
    상세보기
  29. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using same.
    상세보기
  30. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
    상세보기
  31. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
    상세보기
  32. Liao, Chin-I; Chen, Chun-Yu, Epitaxial structure and process thereof for non-planar transistor.
    상세보기
  33. Hokazono, Akira, FinFET comprising a punch-through stopper.
    상세보기
  34. Bauer, Matthias; Gossmann, Hans-Joachim Ludwig; Colombeau, Benjamin, Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth.
    상세보기
  35. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Liu, Yujie; Kim, Sung Hwan; Wang, Lingquan; Zhao, Dalong; Bakhishev, Teymur; Hoffmann, Thomas; Pradhan, Sameer; Duane, Michael, High uniformity screen and epitaxial layers for CMOS devices.
    상세보기
  36. Wang, Jing, Integrated circuit device methods and models with predicted device metric variations.
    상세보기
  37. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
    상세보기
  38. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
    상세보기
  39. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
    상세보기
  40. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
    상세보기
  41. Clark, Lawrence T.; Kidd, David A.; Chen, Chao-Wu, Integrated circuit process and bias monitors and related methods.
    상세보기
  42. Clark, Lawrence T.; Kidd, David A.; Chen, Chao-Wu, Integrated circuit process and bias monitors and related methods.
    상세보기
  43. Zhao, Dalong; Ranade, Pushkar; McWilliams, Bruce, Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same.
    상세보기
  44. Zhao, Dalong; Ranade, Pushkar; McWilliams, Bruce, Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same.
    상세보기
  45. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
    상세보기
  46. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
    상세보기
  47. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachrin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
    상세보기
  48. Brabant, Paul D.; Chung, Keith; He, Hong; Sadana, Devendra K.; Shinriki, Manabu, Low temperature epitaxy of a semiconductor alloy including silicon and germanium employing a high order silane precursor.
    상세보기
  49. Clark, Lawrence T.; Leshner, Samuel, Memory circuits and methods of making and designing the same.
    상세보기
  50. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
    상세보기
  51. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
    상세보기
  52. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
    상세보기
  53. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Liu, Yujie; Kim, Sung Hwan; Wang, Lingquan; Zhao, Dalong; Bakhishev, Teymur; Hoffmann, Thomas; Pradhan, Sameer; Duane, Michael, Method for fabricating a transistor with reduced junction leakage current.
    상세보기
  54. Shifren, Lucian; Ranade, Pushkar; Hoffmann, Thomas; Thompson, Scott E., Method for fabricating multiple transistor devices on a substrate with varying threshold voltages.
    상세보기
  55. Moriya, Atsushi; Nakaiso, Naoharu; Orihashi, Yugo; Murakami, Kotaro, Method of forming silicon layer in manufacturing semiconductor device and recording medium.
    상세보기
  56. Moriya, Atsushi; Nakaiso, Naoharu; Orihashi, Yugo; Murakami, Kotaro, Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium.
    상세보기
  57. Moriya, Atsushi; Nakaiso, Naoharu; Orihashi, Yugo; Murakami, Kotaro, Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium.
    상세보기
  58. Moriya, Atsushi; Nakaiso, Naoharu; Orihashi, Yugo; Murakami, Kotaro, Method of manufacturing semiconductor device, substrate processing apparatus, gas supply system, and recording medium.
    상세보기
  59. Thompson, Scott E.; Ranade, Pushkar; Scudder, Lance; Stager, Charles, Monitoring and measurement of thin film layers.
    상세보기
  60. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
    상세보기
  61. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
    상세보기
  62. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
    상세보기
  63. Kuo, Augustine, Operational amplifier input offset correction with transistor threshold voltage adjustment.
    상세보기
  64. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Leshner, Samuel, Porting a circuit design from a first semiconductor process to a second semiconductor process.
    상세보기
  65. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Leshner, Samuel, Porting a circuit design from a first semiconductor process to a second semiconductor process.
    상세보기
  66. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Leshner, Samuel, Porting a circuit design from a first semiconductor process to a second semiconductor process.
    상세보기
  67. Boling, Edward J., Power up body bias circuits and methods.
    상세보기
  68. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Scudder, Lance; Zhao, Dalong; Bakhisher, Teymur; Pradhan, Sameer, Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom.
    상세보기
  69. Shifren, Lucian; Thompson, Scott E.; Gregory, Paul E., Process for manufacturing an improved analog transistor.
    상세보기
  70. Scudder, Lance S.; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
    상세보기
  71. Scudder, Lance S.; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
    상세보기
  72. Scudder, Lance; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
    상세보기
  73. Scudder, Lance; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
    상세보기
  74. Tien, George; Kidd, David A.; Clark, Lawrence T., SRAM cell layout structure and devices therefrom.
    상세보기
  75. Hoffmann, Thomas; Thompson, Scott E., Semiconductor devices having fin structures and fabrication methods thereof.
    상세보기
  76. Pradhan, Sameer; Zhao, Dalong; Wang, Lingquan; Ranade, Pushkar; Scudder, Lance, Semiconductor devices with dopant migration suppression and method of fabrication thereof.
    상세보기
  77. Shifren, Lucian; Ranade, Pushkar; Sonkusale, Sachin R., Semiconductor structure and method of fabrication thereof with mixed metal types.
    상세보기
  78. Shifren, Lucian; Ranade, Pushkar; Sonkusale, Sachin R., Semiconductor structure and method of fabrication thereof with mixed metal types.
    상세보기
  79. Gregory, Paul E.; Ranade, Pushkar; Shifren, Lucian, Semiconductor structure with improved channel stack and method for fabrication thereof.
    상세보기
  80. Gregory, Paul E.; Shifren, Lucian; Ranade, Pushkar, Semiconductor structure with improved channel stack and method for fabrication thereof.
    상세보기
  81. Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, Semiconductor structure with multiple transistors having various threshold voltages.
    상세보기
  82. Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, Semiconductor structure with multiple transistors having various threshold voltages.
    상세보기
  83. Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, Semiconductor structure with multiple transistors having various threshold voltages.
    상세보기
  84. Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, Semiconductor structure with multiple transistors having various threshold voltages.
    상세보기
  85. Wang, Lingquan; Bakhishev, Teymur; Zhao, Dalong; Ranade, Pushkar; Pradhan, Sameer; Hoffmann, Thomas; Shifren, Lucian; Scudder, Lance, Semiconductor structure with reduced junction leakage and method of fabrication thereof.
    상세보기
  86. Wang, Lingquan; Bakhishev, Teymur; Zhao, Dalong; Ranade, Pushkar; Pradhan, Sameer; Hoffmann, Thomas; Shifren, Lucian; Scudder, Lance, Semiconductor structure with reduced junction leakage and method of fabrication thereof.
    상세보기
  87. Scudder, Lance; Ranade, Pushkar; Stager, Charles; Shifren, Lucian; Zhao, Dalong; Sridharan, U.C.; Duane, Michael, Semiconductor structure with substitutional boron and method for fabrication thereof.
    상세보기
  88. Kidd, David A.; Boling, Edward J.; Agrawal, Vineet; Leshner, Samuel; Kuo, Augustine; Lee, Sang-Soo; Chen, Chao-Wu, Slew based process and bias monitors and related methods.
    상세보기
  89. Kidd, David A.; Boling, Edward J.; Agrawal, Vineet; Leshner, Samuel; Kuo, Augustine; Lee, Sang-Soo; Chen, Chao-Wu, Slew based process and bias monitors and related methods.
    상세보기
  90. Ranade, Pushkar; Shifren, Lucian; Sonkusale, Sachin R., Source/drain extension control for advanced transistors.
    상세보기
  91. Ranade, Pushkar; Shifren, Lucian; Sonkusale, Sachin R., Source/drain extension control for advanced transistors.
    상세보기
  92. Ranade, Pushkar; Shifren, Lucian; Sonkusale, Sachin R., Source/drain extension control for advanced transistors.
    상세보기
  93. Ranade, Pushkar; Shifren, Lucian; Sonkusale, Sachin R., Source/drain extension control for advanced transistors.
    상세보기
  94. Moriya, Atsushi; Nakaiso, Naoharu; Orihashi, Yugo; Murakami, Kotaro, Substrate processing apparatus, apparatus for manufacturing semiconductor device, and gas supply system.
    상세보기
  95. Kidd, David A., Tipless transistors, short-tip transistors, and methods and circuits therefor.
    상세보기
  96. Clark, Lawrence T.; Leshner, Samuel, Tools and methods for yield-aware semiconductor manufacturing process target generation.
    상세보기
  97. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Liu, Yujie; Kim, Sung Hwan; Wang, Lingquan; Zhao, Dalong; Bakhishev, Teymur; Hoffmann, Thomas; Pradhan, Sameer; Duane, Michael, Transistor having reduced junction leakage and methods of forming thereof.
    상세보기
  98. Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, Transistor with threshold voltage set notch and method of fabrication thereof.
    상세보기
  99. Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, Transistor with threshold voltage set notch and method of fabrication thereof.
    상세보기
  100. Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, Transistor with threshold voltage set notch and method of fabrication thereof.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로