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Variable resistance non-volatile memory cells and methods of fabricating same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0775657 (2007-07-10)
등록번호 US7863173 (2010-12-20)
우선권정보 KR-2007-0-2007-0060442(2007-06-20)
발명자 / 주소
  • Kang, Shin-Jae
  • Oh, Gyuhwan
  • Park, Insun
  • Lim, Hyunseok
  • Lim, Nak-Hyun
출원인 / 주소
  • Samsung Electronics Co., Ltd.
대리인 / 주소
    Myers Bigel Sibley & Sajovec, P.A.
인용정보 피인용 횟수 : 9  인용 특허 : 63

초록

Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked

대표청구항

What is claimed is: 1. A method of fabricating an integrated circuit memory cell, comprising:forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening onto an ohmic layer stacked on a conductive structure, wherein an upper portion of the electrode is fo

이 특허에 인용된 특허 (63)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Xu, Daniel, Barrier material encapsulation of programmable material.
  3. Lee, Kong-Soo, Capacitor of an integrated circuit device and method of manufacturing the same.
  4. Liu, Mu-Yi; Fan, Tso-Hung; Chan, Kwang-Yang; Yeh, Yen-Hung; Lu, Tao-Cheng, Chalcogenide memory and method of manufacturing the same.
  5. McTeer Allen, Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with c.
  6. Elkins,Patricia C.; Moore,John T.; Klein,Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  7. Lowrey, Tyler A., Elevated pore phase-change memory.
  8. Gonzalez, Fernando; Turi, Raymond A.; Wolstenholme, Graham R.; Ingalls, Charles L., Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell.
  9. Furkay,Stephen S.; Horak,David V.; Lam,Chung H.; Wong,Hon Sum P., Field emission phase change diode memory.
  10. Chiang, Chien; Dennison, Charles; Lowrey, Tyler, Forming phase change memories.
  11. Scheuerlein,Roy E.; Petti,Christopher J., High bandwidth one time field-programmable memory.
  12. Bailey, Fred D.; Jacobsen, Stuart M., Integrated circuit having a thin film resistor located within a multilevel dielectric between an upper and lower metal interconnect layer.
  13. Lade Robert W. (Fort Myers FL) Benjamin James A. (Waukesha WI) Schutten Herman P. (Milwaukee WI), Lateral bidirectional dual notch shielded FET.
  14. Campbell,Kristy A.; Li,Jiutao; McTeer,Allen; Moore,John T., Layered resistance variable memory device and method of fabrication.
  15. Dennison, Charles, Lower electrode isolation in a double-wide trench.
  16. Dennison, Charles, METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTA.
  17. Hattori Atsuo,JPX, Manufacture of field emission emitter and field emission type device.
  18. Li,Li; Li,Jiutao, Memory cell intermediate structure.
  19. Chiang, Chien; Lee, Jong-Won; Klersy, Patrick, Metal structure for a phase-change memory device.
  20. Koos,Daniel A.; Mayer,Steven T.; Park,Heung L.; Cleary,Timothy Patrick; Mountsier,Thomas, Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage.
  21. Steven T. Harshfield, Method of forming a contact structure in a semiconductor device.
  22. Gill, Manzur; Lowrey, Tyler, Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements.
  23. Harshfield,Steven T.; Wright,David Q., Method of making a memory cell.
  24. Chiang, Chien; Wicker, Guy C., Method to enhance performance of thermal resistor device.
  25. Barth, Hans-Joachim, Method to form selective cap layers on metal features with narrow spaces.
  26. Johnson,Brian G.; Dennison,Charles H., Method to manufacture a phase change memory.
  27. Dennison, Charles, Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby.
  28. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Methods for forming chalcogenide glass-based memory elements.
  29. Park,Jae Hyun; Oh,Jae Hee; Lee,Se Ho; Jeong,Won Cheol, Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other.
  30. Park,Joon sang; Hong,Chang ki; Kim,Sang yong, Methods of fabricating phase change memory elements having a confined portion of phase change material on a recessed contact.
  31. Li,Li; Li,Jiutao, Methods of forming and using memory cell structures.
  32. Hudgens,Stephen J.; Lowrey,Tyler A.; Klersy,Patrick J., Multiple layer phase-change memory.
  33. Happ,Thomas, Phase change memory cell with high read margin at low power operation.
  34. Happ,Thomas, Phase change memory cell with high read margin at low power operation.
  35. Song,Yoon Jong; Lee,Se Ho; Kim,Ki Nam; Lee,Su Youn; Park,Jae Hyun, Phase change memory device and method for forming the same.
  36. Chen, Bomy, Phase change memory device employing thermally insulating voids.
  37. Cho,Byeong Ok; Joo,Suk Ho; Ryoo,Kyung Chang; Byun,Kyung Rae, Phase changeable memory device and method of formation thereof.
  38. Hwang,Young Nam; Lee,Se Ho, Phase changeable memory devices and methods of forming the same in which an upper electrode includes a tip that extends toward a lower electrode.
  39. Dennison, Charles, Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact.
  40. Wolstenholme Graham R. ; Ireland Philip J., Polysilicon pillar diode for use in a non-volatile memory cell.
  41. Ang,Kern Huat; Wang,Ling Sung, Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof.
  42. Agarwala,Birendra N.; Nguyen,Du Binh; Rathore,Hazara Singh, Process for forming a redundant structure.
  43. Gilton,Terry L., Programmable conductor memory cell structure and method therefor.
  44. van Schravendijk,Bart; Mountsier,Thomas W; Sanganeria,Mahesh K; Alers,Glenn B; Shaviv,Roey, Protection of Cu damascene interconnects by formation of a self-aligned buffer layer.
  45. Cowley,Andy; Kaltalioglu,Erdem; Hoinkis,Mark; Stetter,Michael, Reduction of the shear stress in copper via's in organic interlayer dielectric material.
  46. Toda,Haruki; Kubo,Koichi, Resistance change memory device.
  47. Campbell,Kristy A.; Daley,Jon; Brooks,Joseph F., Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication.
  48. Happ,Thomas, Resistive semiconductor element based on a solid-state ion conductor.
  49. Allen McTeer ; Steven T. Harshfield, Selective cap layers over recessed polysilicon plugs.
  50. Jones, Robert E.; Barron, Carole C.; Luckowski, Eric D.; Melnick, Bradley M., Self-aligned magnetic clad write line and its method of formation.
  51. Lung,Hsiang Lan, Self-aligned small contact phase-change memory method and device.
  52. Sagara Kazuhiko (Tokyo JPX) Tamaki Yoichi (Kokubunji JPX) Homma Noriyuki (Kodaira JPX) Nakamura Tohru (Tanashi JPX), Semiconductor device.
  53. Cho,Sung Lae; Hideki,Horii, Semiconductor device and method of fabricating the same.
  54. Lee,Jung hyun; Park,Young soo; Lee,Won tae, Semiconductor memory device and method of fabricating the same.
  55. Cho Deok-Ho (Daejeon KRX) Lee Soo-Min (Daejeon KRX) Han Tae-Hyeon (Daejeon KRX) Ryum Byung-Ryul (Daejeon KRX) Pyun Kwang-Eui (Daejeon KRX), Silicon-silicon-germanium heterojunction bipolar transistor fabrication method.
  56. Lung,Hsiang Lan, Thermally contained/insulated phase change memory device and method (combined).
  57. Gilton, Terry L., Thin film diode integrated with chalcogenide memory cell.
  58. Gilton,Terry L., Thin film diode integrated with chalcogenide memory cell.
  59. Johnson, Mark G., Three-dimensional, mask-programmed read only memory.
  60. Doan Trung, Uniform dielectric layer and method to form same.
  61. Lowrey, Tyler A.; Dennison, Charles H., Utilizing atomic layer deposition for programmable device.
  62. Lung,Hsiang Lan, Vacuum jacket for phase change memory element.
  63. Lowrey,Tyler, Vertical elevated pore phase change memory.

이 특허를 인용한 특허 (9)

  1. Pellizzer, Fabio; Rigano, Antonino; Mariani, Marcello; Benvenuti, Augusto, Method, system and device for recessed contact in memory array.
  2. Pellizzer, Fabio; Rigano, Antonino; Mariani, Marcello; Benvenuti, Augusto, Method, system and device for recessed contact in memory array.
  3. Yang, Jin Seok; Jung, Ha Chang, Phase-change random access memory device and method of manufacturing the same.
  4. Pellizzer, Fabio; Rigano, Antonino; Somaschini, Roberto, Self-aligned interconnection for integrated circuits.
  5. Pellizzer, Fabio; Rigano, Antonino; Somaschini, Roberto, Self-aligned interconnection for integrated circuits.
  6. Ren, Wanchun, Semiconductor device and manufacturing method thereof.
  7. Ren, Wanchun, Semiconductor device and manufacturing method thereof.
  8. Choi, Suk-hun; Bae, Ki-ho; Hong, Yi-koan; Kim, Kyung-hyun; Kim, Tae-hyun; Nam, Kyung-tae; Jeong, Jun-ho, Semiconductor device having a conductive structure including oxide and non oxide portions.
  9. Kanaya, Hiroyuki, Semiconductor storage device and manufacturing method thereof.
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