초록 ▼

A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/

A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of context switches performed in one or more of such paired hardware threads. By doing so, the overall latency of a context switch, where both the context for a process being switched from must be saved, and the context for the process being switched to must be loaded, may be reduced.

대표청구항 ▼

What is claimed is: 1. A method of executing processes in a multithreaded processor of the type including a plurality of hardware threads, wherein the plurality of hardware threads includes first and second hardware threads from among the plurality of hardware threads, the method comprising:concurre

What is claimed is: 1. A method of executing processes in a multithreaded processor of the type including a plurality of hardware threads, wherein the plurality of hardware threads includes first and second hardware threads from among the plurality of hardware threads, the method comprising:concurrently executing processes from among a plurality of processes using the first and second hardware threads;after concurrently executing the plurality of processes using the first and second hardware threads, determining that the second hardware thread is disabled;in response to determining that the second hardware thread is disabled, forming a thread pair between the first and second hardware threads such that the first and second hardware threads collectively execute processes from among the plurality of processes using time-based multiplexing to alternate between executing processes on the first hardware thread and executing processes on the second hardware thread, wherein the first and second hardware threads collectively execute a single process from among the plurality of processes at a time while the thread pair is formed, and wherein forming the thread pair includes:performing a first context switch to initiate execution of a first process among the plurality of processes on the first hardware thread of the thread pair;during execution of the first process on the first hardware thread of the thread pair, loading at least a portion of a context for a second process among the plurality of processes with the second hardware thread of the thread pair;thereafter performing a second context switch to initiate execution of the second process on the second hardware thread of the thread pair, wherein at least a portion of the context for the second process is loaded prior to performing the second context switch;during execution of the second process on the second hardware thread of the thread pair, saving at least a portion of a context for the first process and loading at least a portion of a context for a third process among the plurality of processes with the first hardware thread of the thread pair;thereafter performing a third context switch to initiate execution of the third process on the first hardware thread of the thread pair, wherein at least a portion of the context for the third process is loaded prior to performing the third context switch; andduring execution of the third process on the first hardware thread of the thread pair, saving at least a portion of a context for the second process with the second hardware thread of the thread pair.