초록 ▼

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computa

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

대표청구항 ▼

It is claimed: 1. An adaptive computing engine comprising:a first configurable unit to perform computational functions comprising a first plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed conn

It is claimed: 1. An adaptive computing engine comprising:a first configurable unit to perform computational functions comprising a first plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the computational elements coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a computational function; anda second configurable unit for performing digital signal processing functions comprising a second plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and coupled to each other via a second interconnection network to configure the interconnections between the second plurality of computational elements in response to configuration information to perform a first digital signal processing function, the interconnections between the secondary plurality of computational elements being changeable to reconfigure the second plurality of computational elements in response to different configuration information to perform a second digital signal processing function, the second plurality of computational elements having at least one different type of computational element than those of the first plurality of computational elements.