초록 ▼

A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration c

A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps. The calibration circuit includes a controllable capacitance for receiving a control signal and including an array of switched capacitors selectively activated by the control signal to connect to a first common node that conducts a voltage value depending on the total capacitance value of the activated capacitors; an assessment unit for comparing this voltage value with a reference voltage to output a logic signal that can transition between first and second logic levels; a control and timing unit to receive the logic signal and change the control signal to carry out a subsequent calibration step that is provided at the end of the integration interval during a comparison interval of a preset duration, which allows a transition of the logic signal to occur prior to the beginning of the consecutive calibration step.

대표청구항 ▼

The invention claimed is: 1. A circuit comprising:a controllable capacitance unit structured to receive a control signal and a selected signal and including an array of switched capacitors structured to be selectively activated by the control signal and be connected in response to the selectional si

The invention claimed is: 1. A circuit comprising:a controllable capacitance unit structured to receive a control signal and a selected signal and including an array of switched capacitors structured to be selectively activated by the control signal and be connected in response to the selectional signal to a first common node that is structured to conduct a voltage value that is dependent on a total capacitance of the activated capacitors;an assessment unit adapted to receive and compare the voltage value with a reference voltage and to output a logic signal that, based on a comparison result, can be subjected to a transition between first and second logic levels;a control and timing logic unit adapted to receive the logic signal and to generate the control signal and the selection signal based thereon, the control and timing logic unit structured to change the control signal during calibration cycle in sequential steps using a successive approximation search strategy.