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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0829109 (2007-07-27) |
등록번호 | US7999384 (2011-08-03) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 6 인용 특허 : 502 |
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
What is claimed is: 1. An integrated circuit chip comprising:a silicon substrate;multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;a first dielectric layer over said silicon substrate;a first metallization structure over said first dielectric laye
What is claimed is: 1. An integrated circuit chip comprising:a silicon substrate;multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;a first dielectric layer over said silicon substrate;a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;a second dielectric layer between said first and second metal layers;a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer;a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 30 micrometers; anda second metallization structure over said polymer layer and said first and second contact points, wherein said first contact point is connected to said second contact point though said second metallization structure, wherein said second metallization structure is configured to be wirebonded.
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