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Electromagnetic radiation conduits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
출원번호 US-0724649 (2007-03-14)
등록번호 US8004055 (2011-08-08)
발명자 / 주소
  • Wells, David H.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells St. John P.S.
인용정보 피인용 횟수 : 2  인용 특허 : 68

초록

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include con

대표청구항

The invention claimed is: 1. An electromagnetic radiation conduit, comprising:a first material;a pair of projections projecting upwardly relative to the first material, the pair of projections comprising second material which is compositionally different from the first material;a bridge formed to ex

이 특허에 인용된 특허 (68)

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  11. Forbes,Leonard, Localized strained semiconductor on insulator.
  12. Bryant, Andres; Clark, Jr., William F.; Nowak, Edward J.; Tong, Minh H., Matched transistors and methods for forming the same.
  13. Wells, David H., Memory array buried digit line.
  14. Wells,David H., Memory array buried digit line.
  15. Kobayashi Hikaru,JPX ; Yoneda Kenji,JPX, Method for forming an insulating film on semiconductor substrate surface and apparatus for carrying out the method.
  16. Barlocchi, Gabriele; Villa, Flavio, Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material.
  17. Hsu, Louis L.; Wang, Li-Kong, Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby.
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  25. Fung, Ka Hing, Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET.
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  28. Juengling, Werner, Methods for making nearly planar dielectric films in integrated circuits.
  29. Forbes Leonard, Methods for making silicon-on-insulator structures.
  30. Wells, David H.; Manning, H. Montgomery, Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon.
  31. Wells, David H.; Blomiley, Eric R., Methods of forming transistor devices.
  32. Fucsko, Janos; Wells, David H.; Flynn, Patrick; Lee, Whonchee, Methods of shaping vertical single crystal silicon walls and resulting structures.
  33. William A. Clark ; Mark A. Lemkin ; Thor N. Juneau ; Allen W. Roessig, Microfabricated structures with trench-isolation using bonded-substrates and cavities.
  34. Figura,Thomas A.; Haller,Gordon A., Peripheral gate stacks and recessed array gates.
  35. McFadden, Robert; Kavalieros, Jack; Arghavani, Reza; Barlage, Doug; Chau, Robert, Plasma nitridation for reduced leakage gate dielectric layers.
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  39. Yonehara Takao (Atsugi JPX) Yamagata Kenji (Kawasaki JPX), Process of making semiconductor-on-insulator substrate.
  40. Abatchev,Mirzafer; Wells,David; Zhou,Baosuo; Subramanian,Krupakar M., Protective coating for planarization.
  41. Liang Mong-Song,TWX ; Lee Jin-Yuan,TWX ; Yoo Chue-San,TWX, Pseudo silicon on insulator MOSFET device.
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  43. Deleonibus Simon,FRX, Quantum WELL MOS transistor and methods for making same.
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이 특허를 인용한 특허 (2)

  1. Chen, Jun-Rong; Kuo, Chi-Wen; Huang, Kun-Fu; Chu, Jui-Yi; Fang, Kuo-Lung, Light-emitting diode chip structure and fabrication method thereof.
  2. Koontz, Christopher R.; Wong, Tse E.; Milne, Jason G., Stacked wafer with coolant channels.
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