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Copper-compatible fuse target 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/62
출원번호 US-0805056 (2007-05-22)
발명자 / 주소
  • Naem, Abdalla Aly
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Mark C., Pickering
인용정보 피인용 횟수 : 5  인용 특허 : 39

초록 ▼

A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have been formed, a conductive target, such as an aluminum target, is formed on the copper target structure a

대표청구항 ▼

What is claimed is: 1. A semiconductor structure comprising:a first non-conductive layer having a top surface;a first metallic structure touching and lying over the top surface of the first non-conductive layer;a second metallic structure being spaced apart from the first metallic structure, touchin

이 특허에 인용된 특허 (39)

  1. Lim,Victor Seng Keong; Zhang,Fan; Lam,Jeffrey, Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures.
    상세보기
  2. Xing Guoqiang ; Cerny Glenn A. ; Visokay Mark R., Etchstop for integrated circuits.
    상세보기
  3. Chen,Kuo Tso; Kung,Chen Yueh, Integrated circuit package and method of manufacture.
    상세보기
  4. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
    상세보기
  5. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
    상세보기
  6. Efland Taylor R. ; Cotton Dave ; Skelton Dale J., Ldmos transistor with thick copper interconnect.
    상세보기
  7. Brintzinger, Axel, Manufacturing of a corrosion protected interconnect on a substrate.
    상세보기
  8. Erdeljac John P. ; Hutter Louis Nicholas ; Khatibzadeh M. Ali ; Arch John Kenneth, Metallization outside protective overcoat for improved capacitors and inductors.
    상세보기
  9. Taylor R. Efland ; Dave Cotton ; Dale J. Skelton, Method for LDMOS transistor with thick copper interconnect.
    상세보기
  10. Hui, Chong Chin; Kian, Lee Choon; Chai, Lee Kian, Method for fabricating BOC semiconductor package.
    상세보기
  11. Chen, Linlin; Lu, Jiong-Ping; Xia, Changfeng, Method for forming a conductive copper structure.
    상세보기
  12. Givens John H., Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component.
    상세보기
  13. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.
    상세보기
  14. Towle,Steven; Jones,Martha; Vu,Quat T., Method for packaging a microelectronic device using on-die bond pad expansion.
    상세보기
  15. Morand, Yves; Gobil, Yveline; Demolliens, Olivier; Assous, Myriam, Method for producing a copper connection.
    상세보기
  16. Kumar Nalin (Austin TX), Method of fabricating integrated resistors in high density substrates.
    상세보기
  17. Cheng Peng ; Doyle Brian S., Method of forming contacts.
    상세보기
  18. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect.
    상세보기
  19. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
    상세보기
  20. Efland Taylor R. ; Cotton David ; Skelton Dale J., Method of making a multiple transistor integrated circuit with thick copper interconnect.
    상세보기
  21. Jo,Gyoo Chul, Method of manufacturing a substrate for an electronic device by using etchant and electronic device having the substrate.
    상세보기
  22. Cong,Hai; Siew,Yong Kong; Hsia,Liang Choo, Method to control dual damascene trench etch profile and trench depth uniformity.
    상세보기
  23. Chen Chung-zen (Hsinchu TWX), Moisture guard ring for integrated circuit applications.
    상세보기
  24. Griglione,Michelle D.; Layman,Paul Arthur; Laradji,Mohamed; Thomson,J. Ross; Chaudhry,Samir, Multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material.
    상세보기
  25. Efland Taylor R. ; Skelton Dale J. ; Mai Quang X. ; Williams Charles E., Plastic encapsulation for integrated circuits having plated copper top surface level interconnect.
    상세보기
  26. Efland Taylor R. ; Skelton Dale J. ; Mai Quang X. ; Williams Charles E., Plastic encapsulation for integrated circuits having plated copper top surface level interconnect.
    상세보기
  27. Sawai Akiyoshi,JPX ; Shimamoto Haruo,JPX ; Tachikawa Toru,JPX ; Shibata Jun,JPX, Plastic molded semiconductor package and method of manufacturing the same.
    상세보기
  28. Tzeng Wen-Tsing,TWX ; Chen Yue-Feng,TWX ; Wang Kau-Jan,TWX, Process for controlling oxide thickness over a fusible link using transient etch stops.
    상세보기
  29. Kordic, Srdjan; Torres, Joaquin; Motte, Pascale; Descouts, Brigitte, Process of fabricating an integrated circuit.
    상세보기
  30. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance.
    상세보기
  31. Bojkov,Christo P.; Krumnow,Michael L., Sealing and protecting integrated circuit bonding pads.
    상세보기
  32. Tadayoshi Watanabe JP; Sachiyo Ito JP; Takamasa Usui JP; Hisashi Kaneko JP; Masako Morita JP; Hirokazu Ezawa JP, Semiconductor device and method of manufacturing the same.
    상세보기
  33. Yong,Lois E.; Harper,Peter R.; Tran,Tu Anh; Metz,Jeffrey W.; Leal,George R.; Van Dinh,Dieu, Semiconductor device having a bond pad and method therefor.
    상세보기
  34. Cho,Kang Sik; Park,Chul Sung; Kim,Gyu Chul, Semiconductor device having a fuse connected to a pad and fabrication method thereof.
    상세보기
  35. Hidetoshi Koike JP, Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire.
    상세보기
  36. Abesingha, Buddhika J.; Rincon-Mora, Gabriel A.; Briggs, David D.; Hastings, Roy Alan, Semiconductor device which minimizes package-shift effects in integrated circuits by using a thick metallic overcoat.
    상세보기
  37. Tamaru, Tsuyoshi; Oomori, Kazutoshi; Miura, Noriko; Aoki, Hideo; Oshima, Takayuki, Semiconductor integrated circuit device.
    상세보기
  38. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Thick plated interconnect and associated auxillary interconnect.
    상세보기
  39. Matsunaga, Noriaki; Usui, Takamasa; Ito, Sachiyo, Wiring structure of semiconductor device.
    상세보기

이 특허를 인용한 특허 (5)

  1. Leobandung, Effendi, Chip with programmable shelf life.
    상세보기
  2. Leobandung, Effendi, Chip with programmable shelf life.
    상세보기
  3. Hsu, Louis L.; Tonti, William R.; Yang, Chih-Chao, Interconnect structure containing various capping materials for electrical fuse and other related applications.
    상세보기
  4. Hsu, Louis L.; Tonti, William R.; Yang, Chih-Chao, Interconnect structure containing various capping materials for programmable electrical fuses.
    상세보기
  5. Hsu, Louis L.; Tonti, William R.; Yang, Chih-Chao, Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications.
    상세보기

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