초록 ▼

A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one

A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

대표청구항 ▼

The invention claimed is: 1. A memory system comprising:a memory controller;a plurality of memory modules in communication with the memory controller and with a plurality of memory devices;a plurality of error codes associated with at least two distinct and functionally unique error checking means,

The invention claimed is: 1. A memory system comprising:a memory controller;a plurality of memory modules in communication with the memory controller and with a plurality of memory devices;a plurality of error codes associated with at least two distinct and functionally unique error checking means, each error code associated with a syndrome and a subset of the memory devices, and at least two of the subsets having memory devices in common with each other; andan amalgamating mechanism configured for utilizing at least two non-zero syndromes generated by the distinct and functionally unique error checking means to further extend overall error correction capabilities by enabling additional identification of possible failing memory devices located within intersecting subsets of the memory devices associated with the non-zero syndromes, and for allowing the memory system to continue to run unimpaired in the presence of failing memory devices;wherein the plurality of error codes include a RAID-3 error correction code applied to the memory devices organized in a row across multiple memory modules thus spanning a plurality of memory devices across memory modules and a RAID-6 error correction code applied to the memory devices organized in columns across a single memory module thus spanning only one memory module, where only a single data element is shared between any row and column.