초록 ▼

A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface

A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

대표청구항 ▼

1. A fuse structure comprising: a substrate;a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface;a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip sur

1. A fuse structure comprising: a substrate;a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface;a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface; anda planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and comprising multiple barrier layers of different materials, wherein the entire surface of the planar barrier multilayer assembly facing away from the first chip surface is a planar surface that lies in a single plane and wherein portions of the planar surface are in direct mechanical contact with first and second areas of the metallization layer;wherein the fuse conductive trace, the metallization layer, and the barrier multilayer assembly are disposed such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer. 2. The fuse structure according to claim 1, wherein the fuse conductive trace and the first and the second areas of the metallization layer are planar structures. 3. The fuse structure according to claim 1, wherein the multiple barrier layers are each planar structures. 4. The fuse structure according to claim 1, wherein the multiple barrier layers are each bordering one another. 5. The fuse structure according to claim 1, wherein the planar barrier multilayer assembly comprises a barrier layer and a further barrier layer completely overlapping in a top view in a direction from the first chip surface to the second chip surface. 6. The fuse structure according to claim 1, wherein the multiple barrier layers comprise tantalum, titanium, tantalum nitride or titanium nitride. 7. The fuse structure according to claim 1, wherein the barrier multilayer assembly comprises a first barrier layer of tantalum nitride, a second barrier layer of titanium and a third barrier layer of titanium nitride, wherein the second barrier layer is disposed between the first barrier layer and the third barrier layer. 8. The fuse structure according to claim 7, wherein a thickness of the first barrier layer is higher than a thickness of the second barrier layer and a thickness of the third barrier layer, and the thickness of the third barrier layer is higher than the thickness of the second barrier layer. 9. The fuse structure according to claim 1, wherein a thickness of the barrier multilayer assembly is in a range from 20 nm to 2 μm. 10. The fuse structure according to claim 1, further comprising a passivation disposed on the first chip surface and comprising a recess so that a thickness of the passivation in an area overlapping the fuse conductive trace in a top view of the fuse structure in a direction from the first chip surface to the second chip surface, is smaller than a thickness of the passivation in an area not overlapping the fuse conductive trace in the top view. 11. The fuse structure according to claim 1, further comprising a passivation disposed opposite the fuse conductive trace so that a distance of the fuse conductive trace from a surface of the passivation facing away from the fuse conductive trace is in a range of less than 500 nm. 12. The fuse structure according to claim 1, wherein the fuse conductive trace is implemented for being separated by bombardment with laser energy in a direction from the first chip surface to the second chip surface. 13. A method for manufacturing an electric device with a fuse structure, the method comprising: depositing a first planar area and a second planar area of a metallization layer on a substrate so that the first planar area and the second planar area are separated from each other;forming a planar barrier multilayer assembly comprising multiple barrier layers of different materials, on the planar areas of the metallization layer, wherein the entire surface of the planar barrier multilayer assembly facing the metallization layer is a planar surface that lies in a single plane and wherein portions of the planar surface are in direct mechanical contact with the first and second planar areas of the metallization layer; andcreating a fuse conductive trace on the barrier multilayer assembly so that cutting the fuse conductive trace and the barrier multilayer assembly would result in electrically isolating the first area of the metallization layer from the second area of the metallization layer. 14. The fuse structure according to claim 1, comprising a metal level area on the substrate including a plurality of metal layers, the fuse conductive trace, the metallization layer and the barrier multilayer assembly, wherein the metallization layer is disposed so close to the first chip surface that a ratio of a distance of the metallization layer from a border between the substrate and the metal level area to a distance of the metallization layer from the first chip surface is in a range of more than two. 15. The fuse structure according to claim 1, comprising a counter-electrode on a side of the metallization layer facing away from the first chip surface and electrically isolated from the metallization layer. 16. The fuse structure according to claim 15, wherein the counter-electrode is a planar structure. 17. The fuse structure according to claim 1, wherein the fuse conductive trace is electrically effectively connected to a high-frequency circuit and is adapted to influence an electric behavior of the high-frequency circuit so that the high-frequency circuit comprises a different electric behavior when the fuse conductive trace is cut as compared to when the fuse conductive trace were not cut, wherein the high-frequency circuit is adapted to provide a signal comprising a frequency in a range above 1 MHz. 18. The fuse structure according to claim 1, further comprising a passivation comprising a first passivation layer of an oxide and a second passivation layer of a nitride, wherein the first passivation layer is disposed between the second passivation layer and the fuse conductive trace. 19. The method according to claim 13, wherein creating the fuse conductive trace is followed by creating a structured passivation on the fuse conductive trace and the first and second planar areas of the metallization layer so that a thickness of the passivation in a first sub- area on the fuse conductive trace is lower than a thickness of the passivation in a second sub-area on one of the first and second planar areas of the metallization layer. 20. The method according to claim 13, wherein creating the fuse conductive trace is followed by depositing a passivation in a structured manner on one of the first and second planar areas of the metallization layer and the fuse conductive trace so that the fuse conductive trace is not covered by the passivation at least in one sub-area of the fuse conductive trace.