[미국특허]
Method and apparatus for processing failures during semiconductor device testing
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/28
G06F-011/00
출원번호
US-0046009
(2008-03-11)
등록번호
US-8122309
(2012-02-21)
발명자
/ 주소
Kemmerling, Todd Ryland
출원인 / 주소
FormFactor, Inc.
대리인 / 주소
Kirton & McConkie
인용정보
피인용 횟수 :
0인용 특허 :
85
초록▼
Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on o
Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.
대표청구항▼
1. Apparatus for testing a device under test (DUT), comprising: probes configured to connect electrically with pins of the DUT including pins that are output pins;a memory; andfail capture logic coupled to ones of the test probes and the memory, the fail capture logic configured to allow to be writt
1. Apparatus for testing a device under test (DUT), comprising: probes configured to connect electrically with pins of the DUT including pins that are output pins;a memory; andfail capture logic coupled to ones of the test probes and the memory, the fail capture logic configured to allow to be written into the memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin during a test of the DUT, wherein the fail capture logic is further configured to allow to be written into the memory an indication of only the first failure on a particular individual one of the output pins after an indication of the first failure has been written into the memory for a different individual one of the output pins. 2. The apparatus of claim 1, wherein the fail capture logic includes detection logic and disable logic, wherein the apparatus includes control logic, and wherein: the detection logic is configured to indicate the failures on the output pins of the DUT;the control logic is configured to store failure indications in the memory; andthe disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test. 3. The apparatus of claim 2, wherein the disable logic includes a logic circuit for each of the output pins, the logic circuit including combinatorial logic and a flip-flop. 4. The apparatus of claim 1, wherein the DUT includes multiple devices each having a portion of the output pins. 5. Apparatus for testing a device under test (DUT), comprising: fail capture logic, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory; andanalog-to-digital converter (ADC) logic coupled between the test probes and the fail capture logic, the ADC logic configured to sample voltages of test result signals, the test result signals derived from output signals of the output pins,wherein the fail capture logic includes detection logic and disable logic, wherein the apparatus includes control logic, andwherein: the detection logic is configured to indicate the failures on the output pins of the DUT;the control logic is configured to store failure indications in the memory; andthe disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test. 6. The apparatus of claim 5, wherein the ADC logic is configured to generate codes in response to the sampled voltages and to provide the codes to the detection logic, and wherein the detection logic is configured to indicate the failures in response to the codes. 7. The apparatus of claim 6, wherein the detection logic compares the codes to expected codes to indicate the failures. 8. A test assembly, comprising: a probe card assembly having test probes configured to contact pins of a device under test (DUT);test instruments having test channels coupled to a memory, each of the test channels including: fail capture logic, coupled to ones of the test probes contacting output pins of the pins, to allow to be written into the memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin during a test of the DUT, wherein the fail capture logic allows to be written into the memory an indication of only the first failure on a particular individual one of the output pins after an indication of the first failure has been written into the memory for a different individual one of the output pins. 9. The test assembly of claim 8, wherein the fail capture logic includes detection logic and disable logic, wherein the test instruments include control logic, and wherein the detection logic is configured to indicate the failures on the at least one output pin;the control logic is configured to store failure indications in the memory; andthe disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test. 10. The test assembly of claim 9, wherein the disable logic includes a logic circuit for each of the output pins, the logic circuit including: a flip-flop including a set input coupled to the detection logic and an inverted output; anda logic gate having a first input coupled to the detection logic, a second input coupled to the inverted output of the flip-flop, and an output coupled to the control logic. 11. The test assembly of claim 10, wherein the flip-flop includes a reset input and the test assembly comprises: a register coupled to the reset input. 12. The test assembly of claim 8, wherein the DUT includes multiple devices each having a portion of the output pins. 13. A test assembly, comprising: a probe card assembly having test probes configured to contact pins of a device under test (DUT);test instruments having test channels coupled to a memory, each of the test channels including: fail capture logic, coupled to at least one of the test probes contacting at least one output pin of the pins, to indicate only first failures on the at least one output pin during a test for storage in the memory,wherein the fail capture logic includes detection logic and disable logic, wherein the test instruments include control logic, andwherein: the detection logic is configured to indicate the failures on the at least one output pin;the control logic is configured to store failure indications in the memory; andthe disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test, andwherein each of the test channels further includes:an analog-to-digital converter (ADC) coupled between the fail capture logic and the at least one output pin, the ADC configured to obtain at least one sample of a voltage of a test result signal, the test result signal being derived from an output signal of each of the at least one output pin. 14. The test assembly of claim 13, wherein the ADC is configured to generate at least one code in response to the at least one sample and to provide the at least one code to the detection logic, and wherein the detection logic is configured to indicate the failures in response to the at least one code. 15. The test assembly of claim 14, wherein the detection logic is configured to compare the at least one code to at least one expected code to indicate the failures. 16. A method of testing a device under test (DUT) using a probe card assembly, comprising: applying test signals to input pins of the DUT during a test via test probes supported on the probe card assembly;receiving test result signals derived from output pins of the DUT responsive to the test signals; andstoring in a memory for each of the output pins individually an indication of only a first failure but not any subsequent failure detected on the individual output pin, wherein the storing in a memory stores an indication of the first failure on a particular individual one of the output pins after an indication of the first failure has been stored in the memory for a different individual one of the output pins. 17. The method of claim 16, wherein the step of receiving comprises: sampling voltages of the test result signals to generate codes. 18. The method of claim 17, further comprising: comparing the codes with expected codes to indicate failures on the output pins. 19. The method of claim 18, wherein the step of storing comprises: blocking indications of the failures other than the first failures on the output pins from storage in the memory. 20. The method of claim 16, wherein the DUT includes multiple devices each having a portion of the output pins.
Malladi Deviprasad (Campbell CA) Hanson Lee Frederick (Cupertino CA) Kahahane Jean (Redwood City CA), Apparatus for testing flip chip or wire bond integrated circuits.
Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L. ; Dozier Thomas H. ; Smith William D., Contact carriers (tiles) for populating larger substrates with spring contacts.
Khandros Igor Y. ; Mathieu Gaetar L., Contact structure device for interconnections, interposer, semiconductor assembly and package using the same and method.
Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA) Fulcher Edwin (Palo Alto CA), Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies.
Bogholtz ; Jr. Richard (Mahopac NY) Bosch Louis J. (Hopewell Junction NY) Gower Kevin C. (Wappingers Falls NY) Mitchell Thomas (Cornwall NY), Memory testing system with algorithmic test data generation.
Angulas Christopher G. (Endicott NY) Flynn Patrick T. (Owego NY) Funari Joseph (Vestal NY) Kindl Thomas E. (Endwell NY) Orr Randy L. (Vestal NY), Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using differe.
Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX), Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located.
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y ; Mathieu Gaetan L., Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method.
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.
Okubo Masao (Nishinomiya JPX) Murakami Nobuyuki (Amagasaki JPX) Katahira Kouji (Kikuchi-gun JPX) Iwata Hiroshi (Otokuni-gun JPX) Okubo Kazumasa (Naka-gun JPX), Probe card for maintaining the position of a probe in high temperature application.
Bachelder Thomas W. ; Barringer Dennis R. ; Conti Dennis R. ; Crafts James M. ; Gardell David L. ; Gaschke Paul M. ; Laforce Mark R. ; Perry Charles H. ; Schmidt Roger R. ; Van Horn Joseph J. ; White, Segmented architecture for wafer test and burn-in.
Leas James M. (South Burlington VT) Koss Robert W. (Burlington VT) Walker George F. (New York NY) Perry Charles H. (Poughkeepsie NY) Van Horn Jody J. (Underhill VT), Semiconductor wafer test and burn-in.
Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
Bhaskar Kasi S. (Edmonds WA) Carlson Alden J. (Bothell WA) Couper Alastair N. (Honolulu HI) Lambert Dennis L. (Bothell WA) Scott Marshall H. (Woodinville WA), Test apparatus for electronic assemblies employing a microprocessor.
Faure Louis H. (Poughkeepsie NY) Spoor Terence W. (Marlboro NY), Test probe assembly using buckling wire probes within tubes having opposed overlapping slots.
Beaman Brian Samuel ; Fogel Keith Edward ; Lauro Paul Alfred ; Norcott Maurice Heathcote ; Shih Da-Yuan ; Walker George Frederick, Test probe for high density integrated circuits, methods of fabrication thereof and methods of use thereof.
Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA), Testing and exercising individual, unsingulated dies on a wafer.
Atkins Glen G. (Boise ID) Cohen Michael S. (Boise ID) Mauritz Karl H. (Eagle ID) Shaffer James M. (Boise ID 4), Wafer scale burn-in apparatus and process.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.