초록 ▼

A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive element

A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of electronic devices to higher level circuit structures. The wafer is then divided or “singulated” to provide individual semiconductor dice having their active surfaces covered by the sealing layer. In this manner, the sealing layer initially acts as a stencil for forming the discrete conductive elements and subsequently forms a chip scale package structure to protect the semiconductor dice from the environment.

대표청구항 ▼

1. An electronic device package comprising: a substrate including at least one electronic device with at least one external contact location on a surface thereof;a mask layer on the surface of the substrate having an opening therethrough exposing a central portion and surrounding a periphery of the

1. An electronic device package comprising: a substrate including at least one electronic device with at least one external contact location on a surface thereof;a mask layer on the surface of the substrate having an opening therethrough exposing a central portion and surrounding a periphery of the at least one external contact location;a sealing layer on the mask layer having an aperture therethrough exposing the central portion of the at least one external contact location and a portion of the mask layer surrounding the periphery of the at least one external contact location;a discrete conductive element attached to the at least one external contact location, bounded by and in peripheral contact with the mask layer, spaced inwardly from a periphery of the aperture through the sealing layer, and extending from the surface of the substrate beyond an exposed surface of the sealing layer; anda lateral support layer on the exposed portion of the mask layer within the aperture at least partially surrounding a base portion of the discrete conductive element and laterally supporting the discrete conductive element. 2. The electronic device package of claim 1, wherein the substrate comprises a semiconductor substrate including at least one bond pad for electrical communication with the at least one electronic device. 3. The electronic device package of claim 2, wherein the at least one external contact location comprises the at least one bond pad. 4. The electronic device package of claim 2, further comprising at least one layer of metal over the at least one bond pad. 5. The electronic device package of claim 4, wherein the at least one external contact location comprises a portion of the at least one layer of metal located substantially directly over the at least one bond pad. 6. The electronic device package of claim 4, wherein the at least one external contact location comprises a portion of the at least one layer of metal located remote from the at least one bond pad. 7. The electronic device package of claim 2, wherein the semiconductor substrate comprises a semiconductor wafer bearing a plurality of electronic devices, each electronic device of the plurality of electronic devices having at least one external contact location exposed through the sealing layer. 8. The electronic device package of claim 7, further comprising another sealing layer over a back surface of the semiconductor wafer. 9. The electronic device package of claim 2, wherein the semiconductor substrate comprises an individual semiconductor die and the at least one external contact location is exposed through the sealing layer on an active surface of the semiconductor die. 10. The electronic device package of claim 9, further comprising at least another sealing layer on at least another surface of the semiconductor die. 11. The electronic device package of claim 1, wherein the lateral support layer extends laterally from the discrete conductive element to the sealing layer. 12. The electronic device package of claim 1, wherein the lateral support layer comprises a residual flux material from a solder paste used to form the discrete conductive element. 13. The electronic device package of claim 1, wherein the mask layer and the sealing layer comprise a substantially homogenous structure. 14. The electronic device package of claim 13, wherein the substantially homogenous structure comprises a plurality of superimposed layers of a cured photopolymer. 15. The electronic device package of claim 1, wherein the mask layer comprises one or more superimposed layers of a photocured material. 16. The electronic device package of claim 1, wherein at least the sealing layer comprises a polymer material. 17. The electronic device package of claim 1, wherein the discrete conductive element comprises a volume of at least one metal. 18. An electronic device package comprising: a substrate comprising a semiconductor die with at least one bond pad on an active surface thereof;a mask layer on the active surface surrounding and extending over a peripheral portion of metallization of an external contact location associated with the at least one bond pad with an opening through the mask layer exposing a central portion of the metallization of the external contact location;a sealing layer on the mask layer having an aperture therethrough exposing the central portion of the metallization of the external contact location and a portion of the mask layer surrounding the peripheral portion of the metallization of the external contact location;a discrete conductive element bonded to the central portion of the metallization, bounded by and in peripheral contact with the mask layer, spaced inwardly from a periphery of the aperture through the sealing layer and protruding beyond an exposed surface of the sealing layer; anda support layer on the mask layer within the aperture, surrounding a periphery of a base of the discrete conductive element and laterally supporting the base of the discrete conductive element. 19. The electronic device package of claim 18, wherein the discrete conductive element comprises a solder bump. 20. The electronic device package of claim 18, wherein the sealing layer and the mask layer comprise a substantially homogeneous structure including a plurality of layers. 21. The electronic device package of claim 18, wherein the support layer comprises an epoxy or resin flux material. 22. A wafer-scale electronic device package structure, comprising: a wafer-scale substrate comprising a plurality of semiconductor dice on an active surface thereof, each semiconductor die of the plurality including at least one bond pad on the active surface;a mask layer on the active surface with an opening therethrough exposing a central portion of metallization of an external contact location associated with the at least one bond pad of each semiconductor die, wherein the mask layer surrounds and extends over a peripheral portion of the metallization of the external contact location associated with the at least one bond pad of each semiconductor die;a sealing layer on the mask layer having apertures therethrough, each aperture exposing a central portion of the metallization of each external contact location and the portion of the mask layer surrounding the peripheral portion of the metallization of the external contact location associated with the at least one bond pad of each semiconductor die;a discrete conductive element bonded to an exposed central portion of the metallization of each external contact location, bounded by and in peripheral contact with the mask layer, spaced inwardly from a periphery of the aperture through the sealing layer, and protruding beyond an exposed surface of the sealing layer; anda support layer surrounding a periphery of a base of each discrete conductive element above the exposed portion of the mask layer within each of the apertures laterally supporting each discrete conductive element. 23. The structure of claim 22, wherein the discrete conductive elements comprise solder balls. 24. The structure of claim 22, wherein at least some of the external contact locations are remote from the associated at least one bond pad. 25. The structure of claim 22, wherein the support layer extends laterally from the periphery of the base of each discrete conductive element to a surface of the sealing layer within each aperture.