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This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N− SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (which is proximal to the device's radioactive source) is

This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N− SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (which is proximal to the device's radioactive source) is only 300 nm to 5 nm thick (as an example). In one example, tritium is used as a fuel source. In other embodiments, radioisotopes (such as Nickel-63, promethium or phosphorus-33) may be used. Low energy beta sources, such as tritium, emit low energy beta-electrons that penetrate very shallow distances (as shallow as 5 nm) in semiconductors, including SiC, and can result in electron-hole pair creation near the surface of a semiconductor device rather than pair creation in a device's depletion region. By contrast, as a high energy electron penetrates a semiconductor device surface, such as a diode surface, it produces electron hole-pairs that can be collected at (by drift) and near (by diffusion) the depletion region of the device. This is a betavoltaic device, made of ultra-shallow junctions, which allows such penetration of emitted lower energy electrons, thus, reducing or eliminating losses through electron-hole pair recombination at the surface.

대표청구항 ▼

1. A semiconductor processing method, said method comprising: providing V-groove shaped patterns on both sides of a semiconductor substrate;wherein said semiconductor substrate is an N-type doped semiconductor;dipping said semiconductor substrate into a hot liquid comprising elements Si and C;deposi

1. A semiconductor processing method, said method comprising: providing V-groove shaped patterns on both sides of a semiconductor substrate;wherein said semiconductor substrate is an N-type doped semiconductor;dipping said semiconductor substrate into a hot liquid comprising elements Si and C;depositing P-type doped semiconductor layers on both sides of said semiconductor substrate;pulling out said semiconductor substrate from said hot liquid; andattaching said semiconductor substrate to a piece of radioisotope material. 2. A semiconductor processing method, said method comprising: providing V-groove shaped patterns on both sides of a semiconductor substrate;wherein said semiconductor substrate is a P-type doped semiconductor;dipping said semiconductor substrate into a hot liquid comprising elements Si and C;depositing N-type doped semiconductor layers on both sides of said semiconductor substrate;pulling out said semiconductor substrate from said hot liquid; andattaching said semiconductor substrate to a piece of radioisotope material. 3. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is a lightly-doped material. 4. The semiconductor processing method as recited in claim 1, wherein said radioisotope material is tritium. 5. The semiconductor processing method as recited in claim 1, wherein said radioisotope material is Ni-63. 6. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is from group IV elements. 7. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is from group III-V elements. 8. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is SiC. 9. The semiconductor processing method as recited in claim 1, wherein temperature of said hot liquid is between 400 degrees C. to 1200 degrees C. 10. The semiconductor processing method as recited in claim 1, wherein doping of said semiconductor substrate is smaller than doping of said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate. 11. The semiconductor processing method as recited in claim 1, wherein said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate are highly doped. 12. The semiconductor processing method as recited in claim 1, wherein doping of said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate are highly degenerate. 13. The semiconductor processing method as recited in claim 1, wherein thickness of said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate are in range of 5 nm to 300 nm. 14. The semiconductor processing method as recited in claim 1, wherein said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate are doped with Al. 15. The semiconductor processing method as recited in claim 1, wherein said P-type doped semiconductor layers deposited on both sides of said semiconductor substrate are doped at carrier concentrations of between a range of 1018 cm−3 to a few times 1020 cm−3. 16. The semiconductor processing method as recited in claim 1, wherein relative concentration of said elements Si and C in said hot liquid are 94.5% and 0.5%, respectively, with 5% relative concentration for other elements. 17. The semiconductor processing method as recited in claim 1, said semiconductor processing method further comprises: using aluminum or boron as a dopant. 18. The semiconductor processing method as recited in claim 1, said semiconductor processing method further comprises: adding Ge into said hot liquid. 19. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is based on planar SiC. 20. The semiconductor processing method as recited in claim 1, wherein said semiconductor substrate is based on SiC with pillars.