IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0605222
(2009-10-23)
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등록번호 |
US-8166237
(2012-04-24)
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발명자
/ 주소 |
- Atsatt, Sean R.
- Orthner, Kent
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출원인 / 주소 |
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대리인 / 주소 |
Weaver Austin Villeneuve & Sampson LLP
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인용정보 |
피인용 횟수 :
19 인용 특허 :
1 |
초록
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A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexer
A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.
대표청구항
▼
1. A programmable logic device comprising: a programmable soft-logic portion configurable by a programmed bit stream, said soft-logic portion comprising at least one initiator; and,a hard-logic portion having an interconnect fabric and a memory interface structure, the memory interface structure com
1. A programmable logic device comprising: a programmable soft-logic portion configurable by a programmed bit stream, said soft-logic portion comprising at least one initiator; and,a hard-logic portion having an interconnect fabric and a memory interface structure, the memory interface structure comprising a plurality of input queue modules including a plurality of physical thread pointers and a thread look-up table (LUT), wherein a request from a plurality of logical threads initiated by the at least one initiator is written onto a queue module random access memory (RAM) using the LUT and corresponding physical thread pointer; anda plurality of output data queue modules to temporarily store responses from the RAM until arbitrated onto the interconnect fabric. 2. The programmable logic device of claim 1, wherein the memory interface structure further comprises a scheduler configured to select an ordering of requests for a memory controller. 3. The programmable logic device of claim 1, wherein any number of logical threads can be mapped onto the plurality of physical thread pointers for a queue module. 4. The programmable logic device of claim 1, wherein the plurality of input queue modules include data input queue modules and command input queue modules. 5. The programmable logic device of claim 1, wherein each input queue module further comprises a queue module RAM shared by a plurality of physical threads. 6. The programmable logic device of claim 1, wherein the soft-logic portion further comprises a plurality of queue module RAMs corresponding to the number of input queue modules. 7. The programmable logic device of claim 1, wherein the memory interface structure is configurable using double-data-rate (DDR) memory width and DDR memory frequency. 8. The programmable logic device of claim 1, wherein the memory interface structure is configurable using user logic frequency, number of initiators, number of threads, traffic patterns, quality of service requirements for each logical thread, logical thread association with initiators, and grouping of initiators to share bandwidth. 9. A method of supplying commands and data to a DDR controller on an field programmable gate array (FPGA), the method comprising: generating pointer information for each of a plurality of physical threads in each of a plurality of queue modules implemented as hard-logic on the FPGA;receiving a request with an associated logical thread identification (ID) from one of a plurality of initiators;looking up a physical thread pointer number using the thread ID;generating a queue module RAM address using the physical thread pointer number; and,writing the request to the RAM address; wherein the request is a read command or a write command, and requests for a physical thread pointer comprise a plurality of requests from threads having one or more thread IDs. 10. The method of claim 9, wherein requests for multiple physical thread pointers comprise one or more requests from a thread ID. 11. The method of claim 9, wherein the pointer information for each physical thread of the plurality of physical threads in each queue module of the plurality of queue modules comprises a beginning value, an end value, and an increment value, said beginning value corresponding to a starting location allocated to a physical thread pointer in a queue module RAM, said end value corresponding to an ending location allocated to an end pointer in the queue module RAM, and said increment value corresponding to a memory packet size. 12. The method of claim 9, wherein the plurality of physical threads is 4 physical threads per queue module. 13. The method of claim 9, wherein the plurality of queue modules is 4 queue modules. 14. The method of claim 9, further comprising reordering write data longer than one packet using an initiator and DDR burst widths. 15. A method of communicating data between initiators and a DDR memory in a programmable logic device (PLD), the method comprising: receiving a memory request, the memory request having properties of a thread ID, an initiator ID, a bandwidth requirement, a latency requirement, and a priority code;placing the request using the thread ID in one or more physical threads in one or more queue modules implemented as hard-logic on the PLD;buffering the request in a queue module RAM, said queue module RAM being shared by a plurality of physical threads;scheduling the request using the buffered memory request's properties, other scheduled requests, DDR memory state, and output queues states;submitting the request to a DDR memory controller;receiving a response from the DDR memory;placing the response in an output queue; and,sending the response to its initiator. 16. The method of claim 15, further comprising reordering a write request longer than one packet using an initiator and DDR burst widths. 17. The method of claim 15, wherein buffering the request in a queue module RAM comprises reading pointer information for a physical thread of the one or more physical threads and storing the request at a next pointer location. 18. The method of claim 17, wherein initial pointer information is generated by a PLD designer or a control logic implemented on the PLD as soft-logic. 19. The method of claim 18, wherein the initial pointer information is generated using a bandwidth and backpressure requirements for each physical thread. 20. The method of claim 15, wherein the placing the request in one or more physical threads comprises looking up a physical thread pointer number using the thread ID in a look-up table (LUT), said LUT data is generated by a PLD designer or a control logic implemented on the PLD as soft-logic. 21. The method of claim 15, further comprising converting the request from half data rate to full data rate in the queue module RAM. 22. The method of claim 15, further comprising converting the request from full data rate to half data rate in the output queue.
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