초록 ▼

Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm

Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic design to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist, and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic design into the netlist, technology mapping is performed on a selected portion of the logic design.

대표청구항 ▼

1. A method comprising: receiving at a computing device a first gate-level netlist;generating at the computing device a second gate-level netlist during a first synthesis operation, wherein the first synthesis operation is performed during creation of a logic design, wherein the performance of the f

1. A method comprising: receiving at a computing device a first gate-level netlist;generating at the computing device a second gate-level netlist during a first synthesis operation, wherein the first synthesis operation is performed during creation of a logic design, wherein the performance of the first synthesis operation includes: performing sequential review of a plurality of gates in the first gate-level netlist; andclassifying gates of the plurality of gates according to whether the gates can be implemented on one or more Look Up Tables (LUTs), on hardware resources that perform functions that cannot be implemented on LUTs, or in some other manner;generating a gate implementation of the second gate-level netlist during a second synthesis operation; andmapping the gate implementation to a plurality of resources on an integrated circuit. 2. The method of claim 1, further comprising defining a set of rules for performing a second technology mapping operation during the first synthesis operation, the defined set of rules comprising: (i) performing a first traversal of the logic design; (ii) stopping the first traversal at a first set of origination points other than LUT-based and nonLUT-based origination points in the logic design, wherein origination points of the first set are associated with only one destination; (iii) performing a second traversal of the logic design; (iv) stopping the second traversal at a second set of origination points other than LUT-based and nonLUT-based origination points in the logic design, wherein the origination points of the second set are generated by a gate that has only a third set of LUT-based and nonLUT-based origination points; (v) performing a third traversal of the logic design; (vi) stopping the third traversal at a fourth set of origination points other than a LUT-based and nonLUT-based origination point; (vii) performing a fourth traversal of the logic design; and (viii) stopping the fourth traversal in the logic design at a fifth set of origination points other than LUT-based and nonLUT-based origination points or stopping the fourth traversal at a sixth set of LUT-based origination points with less than a predetermined threshold number of fan-outs. 3. The method of claim 1 wherein said performing sequential review is done during a second technology mapping operation, and wherein said classifying is performed during the second technology mapping operation. 4. The method of claim 1, further comprising sequentially incrementing to a second gate of the plurality of gates when a first gate of the plurality of gates is classified as not requiring implementation on one or more Look Up Tables (LUTs) or on hardware resources that perform functions that cannot be implemented on LUTs. 5. The method of claim 1, further comprising, for each or a subset of the gates of the plurality of gates: generating a first traversed area by traversing the inputs to the gate according to a predefined set of rules;determining a number of inputs to the gate based on the first traversed area;comparing the determined number of inputs to a predetermined threshold;responsive to said predetermined threshold exceeding said determined number of inputs, gradually loosening the predefined set of rules for generating a second traversed area until an expanded cone of adequate size is eventually identified; andresponsive to said determined number of inputs exceeding said predetermined threshold, computing a volume and a number of fan-ins associated with gates classified as requiring implementation on one or more Look Up Tables (LUTs), on hardware resources that perform functions that cannot be implemented on LUTs, or in some other manner, in the traversed area and determining an input boundary of a cone associated with the traversed area. 6. The method of claim 5, further comprising determining whether the computed volume fits into one technology cell or more than one technology cell on the programmable logic device. 7. The method of claim 6, wherein the computed volume includes an expanded cone, wherein when the computed volume extends outside one technology cell, said method further comprising either: mapping the expanded cone to a collection of technology cells using standard synthesis when the expanded cone is deemed safe; orrejecting the expanded cone when a majority of the resources in the expanded cone are firm or soft. 8. The method of claim 7, further comprising incrementing to a gate of the plurality of gates after either mapping the expanded cone to the collection of technology cells or rejecting the expanded cone. 9. The method of claim 5, wherein the computed volume includes a cone, wherein when the cone fits into one technology cell, said method further comprising: determining whether the computed volume is acceptable; andeither: implementing the cone in a single technology cell when the cone is deemed acceptable; orrejecting the cone when the cone is deemed to be unacceptable. 10. The method of claim 9, further comprising comparing the cone to historical data of known acceptable results. 11. The method of claim 9, further comprising incrementing to a gate of the plurality of gates after determining that the cone is acceptable or unacceptable. 12. An integrated circuit comprising: a plurality of hardware resources; anda plurality of connections coupling a portion of the plurality of hardware resources, wherein the plurality of hardware resources is configurable to map to a gate implementation of a first gate-level netlist, wherein the gate implementation is generated by a computing device during performance of a first synthesis operation, wherein the first gate-level netlist is generated from a second gate-level netlist during performance of a second synthesis operation, wherein the second synthesis operation is performed during creation of a logic design, wherein the second gate-level netlist includes a plurality of gates, wherein during the performance the second synthesis operation, gates of the plurality of gates are sequentially reviewed and classified according to whether the gates can be implemented on one or more Look Up Tables (LUTs), on hardware resources that perform functions that cannot be implemented on LUTs, or in some other manner. 13. The integrated circuit of claim 12, wherein the plurality of connections comprises row interconnections and column interconnections. 14. The integrated circuit of claim 12, wherein the portion comprises logic elements, wherein the logic elements comprise one or more look up tables, one or more registers, and one or more adders. 15. The integrated circuit of claim 12, wherein the second gate-level netlist is traversed with a first traversal, a second traversal, and a third traversal, wherein the first traversal is stopped at a first origination point other than a LUT-based and nonLUT-based origination point in the logic design, wherein the first origination point is associated with only one destination, wherein the second traversal is stopped at a second origination point other than a LUT-based and nonLUT-based origination point in the logic design, and wherein the third traversal is stopped at a third origination point other than a LUT-based and nonLUT-based origination point in the logic design or at a fourth LUT-based origination point, wherein the third origination point is associated with less than a pre-determined number of fanouts and the fourth LUT-based origination point is associated with less than the pre-determined number of fanouts. 16. At least one computer readable storage medium having computer program instructions stored thereon that when executed perform a method comprising: receiving at a computing device a first gate-level netlist;generating at the computing device a second gate-level netlist during a first synthesis operation, wherein the first synthesis operation is performed during creation of a logic design, wherein the performance of the first synthesis operation includes: performing sequential review of a plurality of gates in the first gate-level netlist; andclassifying gates of the plurality of gates according to whether the gates can be implemented on one or more Look Up Tables (LUTs), on hardware resources that perform functions that cannot be implemented on LUTs, or in some other manner;generating a gate implementation of the second gate-level netlist during a second synthesis operation; andmapping the gate implementation to a plurality of resources on an integrated circuit. 17. The at least one computer readable storage medium of claim 16, wherein said method further comprises, for each or a subset of the gates of the plurality of gates: generating a first traversed area by traversing the inputs to the gate according to a predefined set of rules;determining a number of inputs to the gate based on the first traversed area;comparing the determined number of inputs to a predetermined threshold;responsive to said predetermined threshold exceeding said determined number of inputs, gradually loosening the predefined set of rules for generating a second traversed area until an expanded cone of adequate size is eventually identified; andresponsive to said determined number of inputs exceeding the predetermined threshold, computing a volume and a number of fan-ins associated with gates classified as requiring implementation on one or more Look Up Tables (LUTs), on hardware resources that perform functions that cannot be implemented on LUTs, or in some other manner, in the first traversed area and determining an input boundary of a cone associated with the traversed area. 18. The at least one computer readable storage medium of claim 17, wherein said method further comprises: determining whether the computed volume fits into one technology cell on the integrated circuit. 19. The at least one computer readable storage medium of claim 17, wherein the computed volume includes a cone, and wherein the computer program instructions are further arranged to perform the following method when the cone fits into one technology cell: determining whether the computed volume is acceptable;implementing the cone in a single technology cell in response to the cone being acceptable; andrejecting the cone in response to the cone being unacceptable.