[특허]Semiconductor package formed within an encapsulation

Semiconductor package formed within an encapsulation 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/56 H01L-021/60
출원번호	US-0760964 (2010-04-15)
등록번호	US-8168475 (2012-05-01)
발명자 / 주소	Choi, Seung-yong Park, Min-hyo
출원인 / 주소	Fairchild Korea Semiconductor, Ltd.
대리인 / 주소	Hiscock & Barclay, LLP
인용정보	피인용 횟수 : 0 인용 특허 : 39

초록 ▼

Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

대표청구항 ▼

1. A method of fabricating a semiconductor package, comprising: forming a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon;forming redistribution layer patterns comprising first and second parts, the first parts facing the bumps and the second parts electrically connected to and spaced from the first parts;forming an organic insulating layer between the redistribution layer patterns and the semiconductor chip, the organic insulating layer having electrically conductive particles distributed in the organic insulating layer to directly contact the top surfaces of first parts of the redistribution layer patterns and the bottom surfaces of the bumpsforming an encapsulation layer on the sacrificial substrate to surround the semiconductor chip on which the redistribution layer patterns are formed; andforming a patterned insulating layer below the exposed redistribution layer patterns, the patterned insulating layer exposing at least parts of the second parts of the redistribution layer patterns. 2. The method of claim 1 further comprising the steps of: providing a sacrificial substrate and forming the redistribution patterns on the sacrificial substrate;disposing the semiconductor chip over the sacrificial substrate on which the redistribution layer patterns are formed, and electrically connecting the bumps to the first parts of the redistribution layer patterns; andremoving the sacrificial substrate so that the redistribution layer patterns are exposed. 3. The method of claim 2, wherein the electrically connecting of the bumps to the first parts of the redistribution layer patterns comprises: interposing the organic insulating layer between the bottom surface of the semiconductor chip and the redistribution layer patterns; andapplying thermo-compression to the semiconductor chip or the redistribution layer patterns so that each of the bumps and each of the redistribution layer patterns commonly contact at least one of the conductive particles. 4. The method of claim 1, wherein in the electrically connecting of the bumps to the first parts of the redistribution layer patterns, the bumps are physically bonded to the first parts of the redistribution layer patterns. 5. The method of claim 4, wherein the physical bonding is achieved using one of heat, pressure, thermosonic waves, and a combination of two or more of these means. 6. The method of claim 2, wherein in the removing of the sacrificial pattern, only the sacrificial substrate is etched without etching the redistribution layer patterns. 7. The method of claim 6, wherein each of the redistribution layer patterns comprise one or more layers from the group consisting of a gold layer, a nickel layer, and a copper layer. 8. The method of claim 6, wherein surfaces of the redistribution layer patterns are surrounded by gold layers. 9. The method of claim 1, wherein surface areas of the second parts of the redistribution layer patterns are greater than surface areas of the first parts thereof. 10. The method of claim 1, wherein a diameter of each of the bumps is in the range of 5 to 200 μm.

이 특허에 인용된 특허 (39)

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