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[미국특허] Semiconductor packaging process using through silicon vias 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/485
출원번호 US-0221204 (2008-07-31)
등록번호 US-8193615 (2012-06-05)
발명자 / 주소
  • Haba, Belgacem
  • Humpston, Giles
  • Margalit, Moti
출원인 / 주소
  • DigitalOptics Corporation Europe Limited
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik, LLP
인용정보 피인용 횟수 : 34  인용 특허 : 30

초록

A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 41

대표청구항

1. A microelectronic unit, comprising: a semiconductor element having a front surface and a rear surface opposite the front surface, a microelectronic semiconductor device adjacent to the front surface, and contacts at the front surface, the semiconductor element having through holes extending from

이 특허에 인용된 특허 (30) 인용/피인용 타임라인 분석

  1. Muramatsu Masaharu,JPX ; Akahori Hiroshi,JPX, Back irradiation type light-receiving device and method of making the same.
  2. Ding, Yi-Chuan; Lee, Xin Hui; Chen, Kun-Ching, Chip scale package and manufacturing method.
  3. Holland Christopher E. (Redwood City CA) Westerberg Eugene R. (Palo Alto CA) Madou Marc J. (Palo Alto CA) Otagawa Takaaki (Fremont CA), Etching method for producing an electrochemical cell in a crystalline substrate.
  4. Belgacem Haba, Forming microelectronic connection components by electrophoretic deposition.
  5. MacIntyre,Donald M., Hermetic wafer scale integrated circuit structure.
  6. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  7. Noma, Takashi; Shinogi, Hiroyuki; Takao, Yukihiro, Manufacturing method of semiconductor device.
  8. Muthukumar, Sriram; Ramanathan, Shriram, Metal-metal bonding of compliant interconnect.
  9. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Method for fabricating chip package.
  10. Tay, Wuu Yean; Tan, Cher Khng Victor, Method for packaging microelectronic devices.
  11. Lee, Hsin-Hui; Lin, Chia-Fu; Su, Chao-Yuan; Chen, Yen-Ming; Ching, Kai-Ming; Chen, Li-Chih, Method of making a wafer level chip scale package.
  12. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  13. Haba, Belgacem, Microelectronic package element and method of fabricating thereof.
  14. Humpston, Giles; Gao, Guilian; Haba, Belgacem, Microelectronic packages and methods therefor.
  15. Akram Salman, Multi chip semiconductor package and method of construction.
  16. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Haba, Belgacem; Oganesian, Vage, Packaged semiconductor chips.
  17. Badehi Pierre,ILX, Process for manufacturing solder leads on a semiconductor device package.
  18. Yamada, Yuichiro; Hamatani, Tsuyoshi, Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device.
  19. Wood, Alan G.; Doan, Trung Tri, Semiconductor component with backside contacts and method of fabrication.
  20. Katagiri, Mitsuaki; Shirai, Yuji; Nishi, Kunihiko; Ohnishi, Takehiro, Semiconductor integrated circuit device and its manufacturing method.
  21. Jun Andoh JP; Yoshihiro Morii JP; Toshio Kobayashi JP; Akio Yashiba JP; Hiroshi Takemoto JP; Takeshi Sano JP; Tsutomu Sakatsu JP, Solid-state imaging device and method of production of the same.
  22. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Stackable chip scale semiconductor package with mating contacts on opposed surfaces.
  23. Hsu Chen-Chung (Taichung TWX), Three-dimensional multichip package.
  24. Hedler, Harry; Meyer, Thorsten; Vasquez, Barbara, Transfer wafer level packaging.
  25. Wen-Ken Yang TW, Wafer level package and the process of the same.
  26. Chang, Tae-Sub; Lee, Dong-Ho; Son, Min-Young, Wafer level package including ground metal layer.
  27. Geyer,Stefan, Wafer level packages for chips with sawn edge protection.
  28. Kung Ling-Chen,TWX ; Lin Jyh-Rong,TWX ; Chen Kuo-Chuan,TWX, Wafer level packaging method and packages formed.
  29. Lin Mou-Shiung,TWX, Wafer scale packaging scheme.
  30. Umetsu, Kazushige; Kurashima, Yohei; Amako, Jun, Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument.

이 특허를 인용한 특허 (34) 인용/피인용 타임라인 분석

  1. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  2. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  3. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  4. Fay, Owen R.; Kirby, Kyle K.; England, Luke G.; Gandhi, Jaspreet S., Interconnect assemblies with probed bond pads.
  5. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  6. Fay, Owen R.; Kirby, Kyle K.; England, Luke G.; Gandhi, Jaspreet S., Methods for forming interconnect assemblies with probed bond pads.
  7. Greeley, Joseph Neil; Goodner, Duane M.; Bhat, Vishwanath; Antonov, Vassil N.; Raghu, Prashant, Methods of forming capacitors.
  8. Oganesian, Vage; Haba, Belgacem; Mitchell, Craig; Mohammed, Ilyas; Savalia, Piyush, Methods of forming semiconductor elements using micro-abrasive particle stream.
  9. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Microelectronic elements having metallic pads overlying vias.
  10. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Microelectronic elements with rear contacts connected with via first or via middle structures.
  11. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  12. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  13. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  14. Greeley, Joseph Neil; Goodner, Duane M.; Bhat, Vishwanath; Antonov, Vassil N.; Raghu, Prashant, Multi-material structures and capacitor-containing semiconductor constructions.
  15. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  16. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  17. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  18. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  19. Haba, Belgacem; Humpston, Giles; Margalit, Moti, Semiconductor packaging process using through silicon vias.
  20. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.
  21. Haba, Belgacem; Oganesian, Vage; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Stacked microelectronic assembly having interposer connecting active chips.
  22. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  23. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  24. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages with plural active chips.
  25. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  26. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  27. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assemby with TSVS formed in stages and carrier above chip.
  28. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  29. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  30. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  31. Uzoh, Cyprian; Oganesian, Vage; Mohammed, Ilyas, Systems and methods for producing flat surfaces in interconnect structures.
  32. Uzoh, Cyprian; Oganesian, Vage; Mohammed, Ilyas, Systems and methods for producing flat surfaces in interconnect structures.
  33. Uzoh, Cyprian; Oganesian, Vage; Mohammed, Ilyas, Systems and methods for producing flat surfaces in interconnect structures.
  34. Uzoh, Cyprian; Oganesian, Vage; Mohammed, Ilyas, Systems and methods for producing flat surfaces in interconnect structures.

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