|국가/구분||United States(US) Patent 등록|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 1 인용 특허 : 48|
A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer a...
1. An apparatus comprising: a delay chain to generate a plurality of delayed signals from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the apparatus;a multiplexer to sequentially couple selected delayed signals of the plurality of delayed signals to an output line with a pre-charge voltage that is lower than the supply voltage of the apparatus; anda pre-...