초록 ▼

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain tap

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

대표청구항 ▼

1. An apparatus comprising: a delay chain to generate a plurality of delayed signals from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signa

1. An apparatus comprising: a delay chain to generate a plurality of delayed signals from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the apparatus;a multiplexer to sequentially couple selected delayed signals of the plurality of delayed signals to an output line with a pre-charge voltage that is lower than the supply voltage of the apparatus; anda pre-charge controller including: an input coupled to the output line; andan output responsive to each edge of the selected delayed signals;wherein the pre-charge controller is configured to vary a delay between edges of the selected delayed signals, and wherein the pre-charge voltage is selected to reduce a switch delay time from the taps of the delay chain to the output line compared to a supply voltage delay time based on the supply voltage, and the multiplexer is configured based on the reduced switch delay time to couple a clock edge at the second tap of the delay chain to the output line after coupling the clock edge at the first tap of the delay chain to the output line before the clock edge reaches the second tap of the delay chain. 2. The apparatus of claim 1, wherein the pre-charge controller is configured to couple the pre-charge voltage to the multiplexer. 3. The apparatus of claim 1, wherein the pre-charge controller is configured to control a coupling between the pre-charge voltage and the multiplexer. 4. The apparatus of claim 1, wherein: the delay chain comprises a plurality of current controlled elements and a plurality of taps, each tap being coupled to one of the current controlled elements; andthe delay chain is coupled to receive a clock signal to generate the plurality of delayed signals from the current controlled elements, each delayed signal comprising a signal edge, the multiplexer to couple one of the signal edges from one of the taps to the output line. 5. The apparatus of claim 4, further comprising a state machine coupled to select taps in the delay chain by controlling the multiplexer through a register to generate a pulse train on the output line with delays between pulses in the pulse train representing encoded data. 6. The apparatus of claim 1, wherein the pre-charge voltage is 1.8 volts and the supply voltage is 2.85 volts. 7. An apparatus comprising: an output;a delay chain to generate a plurality of delayed signal edges from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signal edges including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the apparatus;a multiplexer coupled to select one of the delayed signal edges; anda pre-charge circuit having an input coupled to the output, the pre-charge circuit configured to complete a pulse started by the selected one of the plurality of delayed signal edges;a pre-charge transistor having a first node directly coupled to a pre-charge voltage, a second node coupled to the output, and a control node coupled to the output of the pre-charge circuit, the pre-charge transistor configured to couple and decouple the output to the pre-charge voltage responsive to the output of the pre-charge circuit; andwherein the pre-charge voltage is lower than the supply voltage of the apparatus, and wherein the pre-charge voltage is selected to reduce a switch delay time from the taps of the delay chain to the output compared to a supply voltage delay time based on the supply voltage, and the multiplexer is configured based on the reduced switch delay time to couple a clock edge at the second tap of the delay chain to the output line after coupling the clock edge at the first tap of the delay chain to the output line before the clock edge reaches the second tap of the delay chain. 8. The apparatus of claim 7, wherein the pre-charge transistor is configured to couple the pre-charge voltage to the multiplexer. 9. The apparatus of claim 7, wherein the multiplexer is coupled between the delay chain and an output line to couple the selected delayed signal edge from the delay chain to the output line. 10. The apparatus of claim 7, wherein the pre-charge voltage is 1.8 volts and the supply voltage is 2.85 volts. 11. A method comprising: generating a plurality of delayed signals in a delay chain in an integrated circuit from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the integrated circuit;sequentially coupling selected delayed signals of the plurality of delayed signals to an output line of the integrated circuit using a multiplexer;receiving the selected delayed signals at an input of a pre-charge circuit;coupling the output line of the integrated circuit with a pre-charge voltage that is lower than the supply voltage of the integrated circuit in response to an output of the pre-charge circuit, wherein the pre-charge voltage is selected to reduce a switch delay time from the taps of the delay chain to the output line compared to a supply voltage delay time based on the supply voltage; anduncoupling the output line from the pre-charge voltage in a time based on the reduced switch delay time to couple a clock edge at the second tap of the delay chain to the output line after coupling the clock edge at the first tap of the delay chain to the output line before the clock edge reaches the second tap of the delay chain. 12. The method of claim 11, wherein coupling the output line further comprises: pre-charging the multiplexer with the pre-charge voltage. 13. The method of claim 11, wherein generating a plurality of delayed signals further comprises: generating a plurality of delayed signal edges from a plurality of taps between a plurality of delay elements in the delay chain; andcontrolling a delay interval of each delay element with a current mirror. 14. The method of claim 11, further comprising controlling the multiplexer with a state machine through a register to select taps in the delay chain to generate a pulse train on the output line with delays between pulses in the pulse train representing the encoded data. 15. The method of claim 11, wherein the pre-charge voltage is 1.8 volts and the supply voltage is 2.85 volts.