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Selectable delay pulse generator

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03H-011/26   
미국특허분류(USC) 327/276; 327/277
출원번호 US-0510200 (2009-07-27)
등록번호 US-8193846 (2012-06-05)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 1  인용 특허 : 48
초록
▼

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer a...

대표
청구항
▼

1. An apparatus comprising: a delay chain to generate a plurality of delayed signals from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the apparatus;a multiplexer to sequentially couple selected delayed signals of the plurality of delayed signals to an output line with a pre-charge voltage that is lower than the supply voltage of the apparatus; anda pre-...

이 특허에 인용된 특허 (48)

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  35. Murakami Daisuke (Kanagawa JPX) Kuwabara Tadao (Kanagawa JPX). Pulse signal generator having delay stages and feedback path to control delay time. USP1993095243240.
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  46. Conn Robert O. ; Alfke Peter H.. User-controlled delay circuit for a programmable logic device. USP2000116150863.
  47. Danner ; Jr. Harold J. (117 Oravetz Rd. Auburn WA 98002) Holmes William B. (15454 - 139th Ave. SE. Renton WA 98058) Barron Wesley (5000 Dairy Rd. Kamloops ; B.C. CAX). Vacuum insulated container. USP1994055316171.
  48. DeLisle Francis A. (Wappingers Falls NY) Jacoutot Alfred M. (Winooski VT). Variable self-correcting digital delay circuit. USP1993085237224.

이 특허를 인용한 특허 피인용횟수: 1

  1. Ahn, Seung-Joon; Lee, Jong-Chern. Open loop type delay locked loop and method for operating the same. USP2013078482331.

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