초록 ▼

Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The syst

Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

대표청구항 ▼

1. A method for processing packets in a system that comprises a plurality of interconnected processor cores, the method comprising: receiving packets into a plurality of queues;associating at least some nodes at a first level in a hierarchy of nodes with respective ones of the plurality of queues, a

1. A method for processing packets in a system that comprises a plurality of interconnected processor cores, the method comprising: receiving packets into a plurality of queues;associating at least some nodes at a first level in a hierarchy of nodes with respective ones of the plurality of queues, and associating at least some of the nodes at a second level in the hierarchy with respective rates of transfer;mapping a first set of nodes at the first level in the hierarchy to a plurality of processor cores based on at least one rate associated with a node at the second level in the hierarchy, with a first subset of nodes in the first set being mapped to a first group of processor cores and a second subset of nodes in the first set being mapped to a second group of processor cores, and with a first processor core in the first group being responsible for a first function for the nodes in the first subset, a second processor core in the first group being responsible for a second, different function for the nodes in the first subset, a first processor core in the second group being responsible for the first function for the nodes in the second subset, and a second processor core in the second group being responsible for the second, different function for the nodes in the second subset; andprocessing the packets in processor cores including the mapped processor cores according to the hierarchy. 2. The method of claim 1, wherein each node in the first set is associated with a rate-limit, and mapping the first set of nodes to the plurality of processor cores comprises selecting a plurality of nodes according to a sum of the rate-limits of the plurality of nodes that provides a maximum rate at which at least portions of packets can be transmitted from at least one processor core in each of the groups. 3. The method of claim 2, wherein the rate associated with a node at the second level in the hierarchy comprises a rate associated with a node mapped to a higher-level processor core that receives packets from at least one processor core in each of the groups. 4. The method of claim 3, wherein the sum of the rate-limits is no greater than the rate associated with the node mapped to the higher-level processor core. 5. The method of claim 2, further comprising mapping a second set of nodes at the first level in the hierarchy, each associated with at least one of the plurality of queues, to one or more groups of processor cores different from the first and second groups of processor cores. 6. The method of claim 5, wherein processing the packets comprises passing at least a portion of at least some of the packets received in the plurality of queues associated with the nodes of the second set from a processor core in the one or more groups to the first processor core in the first group according to a rate shaper that smoothes traffic flow to remove burstiness of packets arriving in the plurality of queues associated with the nodes of the second set. 7. The method of claim 1, wherein the mapping occurs before the packets have been received into the plurality of queues. 8. The method of claim 1, wherein at least some of the mapping occurs after at least some of the packets have been processed in processor cores that have already been mapped. 9. The method of claim 1, wherein processing the packets comprises passing at least a portion of at least some of the packets received in the plurality of queues from a processor core mapped to a node associated with at least one of the plurality of queues through processor cores mapped to a series of nodes at different levels of the hierarchy. 10. The method of claim 9, wherein a portion of a packet is passed from a processor core mapped to a first node at the first level to a processor core mapped to a second node at the second level only when one or more credit-related conditions are met. 11. The method of claim 10, wherein a first credit-related condition comprises the first node receiving flow credits from the second node according to an ability of the second node to receive additional packet portions from the first node. 12. The method of claim 11, wherein a second credit-related condition comprises the first node receiving rate credits based on a rate limit that indicates a maximum transfer rate for the first node. 13. The method of claim 9, wherein passing at least a portion of a packet comprises passing a packet descriptor that includes a number of bytes of data in the corresponding packet and a pointer to the packet. 14. The method of claim 9, wherein passing at least a portion of a packet from a processor core mapped to a first node to a processor core mapped to a second node comprises passing a portion of the packet over a network connection between the processor cores. 15. The method of claim 14, wherein passing a portion of the packet over a network connection between the processor cores comprises passing the portion of the packet over a path that includes one or more processor cores between the processor core mapped to the first node and the processor core mapped to the second node. 16. The method of claim 1, wherein the first function comprises a scheduling function in which packets are processed according to a credit-based permission system. 17. The method of claim 16, wherein the second function comprises a rate-limiting function in which an average rate at which packets are processed is limited. 18. The method of claim 1, wherein the number of groups of processor cores to which respective subsets of nodes are mapped is based on a number of packets per second that each group of processor cores is able to process. 19. The method of claim 1, wherein the processor cores in each group of processor cores are adjacent within an interconnection network of the plurality of interconnected processor cores. 20. A system, comprising: a plurality of processor cores interconnected by an interconnection network; andinformation for configuring the system to execute instructions to receive packets into a plurality of queues;associate at least some nodes at a first level in a hierarchy of nodes with respective ones of the plurality of queues, and associating at least some of the nodes at a second level in the hierarchy with respective rates of transfer;map a first set of nodes at the first level in the hierarchy to a plurality of processor cores based on at least one rate associated with a node at the second level in the hierarchy, with a first subset of nodes in the first set being mapped to a first group of processor cores and a second subset of nodes in the first set being mapped to a second group of processor cores, and with a first processor core in the first group being responsible for a first function for the nodes in the first subset, a second processor core in the first group being responsible for a second, different function for the nodes in the first subset, a first processor core in the second group being responsible for the first function for the nodes in the second subset, and a second processor core in the second group being responsible for the second, different function for the nodes in the second subset; andprocess the packets in processor cores including the mapped processor cores according to the hierarchy. 21. The system of claim 20, further comprising a memory for storing the information for configuring the system. 22. The system of claim 20, wherein the first function comprises a scheduling function in which packets are processed according to a credit-based permission system. 23. The system of claim 22, wherein the second function comprises a rate-limiting function in which an average rate at which packets are processed is limited. 24. The system of claim 20, wherein the interconnection network comprises a two-dimensional network. 25. The system of claim 20, wherein the interconnection network comprises a bus network, a ring network, a mesh network, or a crossbar switch network. 26. The system of claim 20, wherein each of the plurality of processor cores corresponds to a tile on an integrated circuit, each tile comprising: a computation unit; anda switch including switching circuitry to forward data received over data paths of the interconnection network from other tiles to the computation unit and to switches of other tiles, and to forward data received from the computation unit to switches of other tiles. 27. The system of claim 26, wherein the computation unit comprises a pipelined processor and the switch is coupled to a plurality of pipeline stages of the pipelined processor. 28. The system of claim 27, wherein at least one port of the switch is mapped to a register name space of the pipelined processor.