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A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences betwe

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

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1. An electronic circuit comprising: a sensor configured to convert photons into an output signal; anda processing module including at least two layers, wherein each of the at least, two layers comprises a channel that is configured to convert the output signal into an image data set including at le

1. An electronic circuit comprising: a sensor configured to convert photons into an output signal; anda processing module including at least two layers, wherein each of the at least, two layers comprises a channel that is configured to convert the output signal into an image data set including at least one digital bit;wherein each channel includes: a reference insert circuit configured to insert a user-defined reference point at a position in the image data set; anda reference point synchronization circuit configured to synchronize the user-defined reference point with another user-defined reference point from another layer. 2. The electronic circuit of claim 1, further comprising a compressible conductor configured to electrically connect the electronic circuit to an external circuit. 3. The electronic circuit of claim 2, further comprising an interposer layer including a dielectric layer, wherein the compressible conductor extends through the dielectric layer. 4. The electronic circuit of claim 1, further comprising a first-in, first-out (FIFO) shift register configured to store the image data set. 5. The electronic circuit of claim 1, wherein each of the at least two layers comprises a readout electronic integrated circuit (ROIC). 6. The electronic circuit of claim 5, further comprising a conductive trace configured to route an electrical signal from the ROIC to an access lead disposed at an edge of one of the at least two layers. 7. The electronic circuit of claim 6, further comprising a T-connect structure configured to electrically connect the access lead to an output of the sensor. 8. The electronic circuit of claim 1, wherein the reference point synchronization circuit comprises a field-programmable gate array (FPGA). 9. The electronic circuit of claim 1, wherein all the channels of the at least two layers are defined upon a single integrated circuit chip. 10. The electronic circuit of claim 1, wherein each channel of the at least two layers is defined upon a separate integrated circuit chip. 11. The electronic circuit of claim 1, wherein the sensor comprises a focal plane array having a plurality of photo-detector pixels configured to detect reflected photons. 12. The electronic circuit of claim 1, further comprising comparator circuitry configured to determine if a pulse of the output signal exceeds a predetermined threshold. 13. The electronic circuit of claim 12, wherein the predetermined threshold is programmable. 14. The electronic circuit of claim 1, wherein the user-defined reference point comprises a user-defined bin logic state, and wherein the reference insert circuit is further configured to insert the user-defined bin logic state in a preselected bin circuit of a FIFO shift register. 15. The electronic circuit of claim 1, wherein the reference point synchronization circuit is configured to accommodate for timing differences between its respective layer and the other layer by synchronizing the user-defined reference point with the other user-defined reference point from the other layer. 16. An electronic circuit comprising: a sensor configured to convert photons into an output signal; anda processing module including a stack of integrated circuit layers, wherein a first layer from the stack of integrated circuit layers comprises: a channel configured to convert the output signal into an image data set including at least one digital bit;a storage circuit configured to store the image data set;a reference insert circuit configured to selectively insert a user-defined reference point at a pre-determined position in the image data set; anda reference point synchronization circuit configured to synchronize the image data set with another image data set from another layer of the stack of integrated circuit layers using the user-defined reference point. 17. The electronic circuit of claim 16, further comprising an interposer layer including a dielectric layer and a compressible conductor, wherein the compressible conductor extends through the dielectric layer and is configured to electrically connect the electronic circuit to an external circuit. 18. The electronic circuit of claim 16, wherein the storage circuit comprises a first-in, first-out (FIFO) shift register. 19. The electronic circuit of claim 16, wherein the first layer further comprises a readout electronic integrated circuit (ROIC). 20. The electronic circuit of claim 19, further comprising a conductive trace configured to route an electrical signal from the ROIC to an access lead disposed at an edge of the first layer. 21. The electronic circuit of claim 20, further comprising a T-connect structure configured to electrically connect the access lead to an output of the sensor. 22. The electronic circuit of claim 16, wherein the reference point synchronization circuit comprises a field-programmable gate array (FPGA). 23. The electronic circuit of claim 16, wherein the sensor comprises a focal plane array having a plurality of photo-detector pixels configured to detect reflected photons. 24. The electronic circuit of claim 16, further comprising comparator circuitry configured to determine if a pulse of the output signal exceeds a programmable predetermined threshold. 25. A method comprising: converting detected photons into an output signal;converting the output signal into an image data set at a first integrated circuit layer of a processing module, wherein the image data set includes at least one digital bit;inserting a first user-defined reference point at a position in the image data set; andsynchronizing the first user-defined reference point with a second user-defined reference point associated with a second integrated circuit layer of the processing module. 26. The method of claim 25, further comprising detecting photons reflected from a target. 27. The method of claim 25, further comprising performing a histogram calculation at a field-programmable gate array (FPGA) to remove jitter associated with operation of the first integrated circuit layer or the second integrated circuit layer. 28. The method of claim 25, further comprising storing the image data set in a first-in, first-out (FIFO) shift register. 29. The method of claim 28, further comprising multiplexing the stored image data set to external processing circuitry. 30. The method of claim 29, wherein the external processing circuitry is electrically connected to the processing module via a compressible conductor disposed in an interposer layer. 31. The method of claim 25, further comprising determining via comparator circuitry if a pulse of the output signal exceeds a predetermined threshold. 32. The method of claim 31, further comprising storing an output of the comparator circuitry in a FIFO shift register. 33. The method of claim 25, wherein said synchronizing the first user-defined reference point comprises realigning the inserted first user-defined reference point with the second user-defined reference point to shift the image data set corresponding to the first integrated circuit layer into alignment with another image data set corresponding to the second integrated circuit layer.