IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0314878
(2008-12-18)
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등록번호 |
US-8198753
(2012-06-12)
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발명자
/ 주소 |
|
출원인 / 주소 |
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대리인 / 주소 |
Finnegan, Henderson, Farabow, Garrett & Dunner LLP
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인용정보 |
피인용 횟수 :
2 인용 특허 :
9 |
초록
▼
A method of operating a power system is provided. The power system has a plurality of generator sets and a bus. The method monitors the bus and generator sets disconnected from the bus. The method supplies to a control device information associated with the operating state of each of the generator s
A method of operating a power system is provided. The power system has a plurality of generator sets and a bus. The method monitors the bus and generator sets disconnected from the bus. The method supplies to a control device information associated with the operating state of each of the generator sets and the bus. The method determines a relative frequency mismatch, multiplied by a first weight factor, and a relative phase mismatch, multiplied by a second weight factor, between the frequency and phase of the bus and a generator, and generates a frequency speed bias and a phase speed bias for the generator. The method adds the frequency and phase speed biases to form a total speed bias and connects the generator to the bus when the voltage, frequency, and phase of the generator are within a permissible range of the bus.
대표청구항
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1. A method of operating a power system, the power system including a plurality of generator sets and a bus, each generator set including at least a generator and an engine, the method comprising: monitoring at least one generator set that is disconnected from the bus;monitoring the bus;supplying, t
1. A method of operating a power system, the power system including a plurality of generator sets and a bus, each generator set including at least a generator and an engine, the method comprising: monitoring at least one generator set that is disconnected from the bus;monitoring the bus;supplying, to a control device, information associated with the operating state of each of the generator sets and information associated with the bus;determining a relative frequency mismatch between the frequency of the bus and the frequency of the generator;multiplying the relative frequency mismatch between the frequency of the bus and the frequency of the generator by a first weight factor to generate a frequency speed bias for the generator set;determining a relative phase mismatch between the phase of the bus and the phase of the generator;multiplying the relative phase mismatch between the phase of the bus and the phase of the generator by a second weight factor to generate a phase speed bias for the generator set;adding the frequency speed bias and the phase speed bias to form a total speed bias; andconnecting the generator set to the bus when the voltage, frequency, and phase of the generator are within a permissible range of the voltage, frequency, and phase of the bus. 2. The method of claim 1, wherein the first weight factor is a value between one and zero and the second weight factor also is a value between one and zero, wherein if the first weight factor increases, the second weight factor may decrease and if the first weight factor decreases, the second weight factor may increase. 3. The method of claim 2, further including setting the first weight factor equal to one if the relative frequency mismatch between the frequency of the bus and the frequency of the generator is above a first frequency error value, and setting the first weight factor equal to zero if the relative frequency mismatch between the frequency of the bus and the frequency of the generator is below a second frequency error value. 4. The method of claim 3, wherein the first frequency error value is between five hertz and five-tenths of a hertz, and the second frequency error value is between one hertz and one-tenth of a hertz. 5. The method of claim 1, further including initiating the frequency speed bias and the phase speed bias to generate the total speed bias when the relative frequency mismatch between the frequency of the bus and the frequency of the generator is below a value with a range between ten hertz and one hertz. 6. The method of claim 1, wherein determining the relative frequency mismatch between the frequency of the bus and the frequency of the generator includes comparing the outputs of a first integrator with an input of a fixed value based on whether the generator instantaneous voltage is positive, and a second integrator with an input of a fixed value based on whether the bus instantaneous voltage is positive, to determine the relative frequency mismatch of the generator and the bus. 7. The method of claim 1, further including restricting the maximum level of the frequency speed bias and restricting the maximum level of the phase speed bias. 8. The method of claim 1, wherein determining the relative phase mismatch between the phase of the bus and the phase of the generator includes determining whether the phase of the generator lags or leads the phase of the bus and applying XOR logic to a logic signal of the generator voltage waveform and a logic signal of the bus voltage waveform. 9. The method of claim 1, further including controlling a plurality of generators with a synchronization and load sharing control including a plurality of control devices, each control device being associated with one of the plurality of generators. 10. A power system, comprising: a bus;a plurality of generator sets operable to supply electricity to an electric power load;a generator set including at least a generator and an engine;a frequency speed bias circuit, configured to input a voltage waveform from the generator, input a voltage waveform from the bus, generate a relative frequency mismatch, multiply the relative frequency mismatch by a first weight factor, and output a frequency speed bias from a first PID controller;a phase speed bias circuit, configured to input a voltage waveform from the generator, input a voltage waveform from the bus, generate a signal proportional to a phase error between the generator and the bus, multiply the signal proportional to the phase error between the generator and the bus by a second weight factor, and output a phase speed bias from a second PID controller;a total speed bias circuit, configured to add the frequency speed bias and the phase speed bias to form a total speed bias; anda generator breaker configured to connect the generator to the bus when the voltage, frequency, and phase of the generator are within a permissible range of the voltage, frequency, and phase of the bus. 11. The power system of claim 10, wherein the first weight factor is a value between one and zero and the second weight factor also is a value between one and zero, wherein if the first weight factor increases, the second weight factor may decrease and if the first weight factor decreases, the second weight factor may increase. 12. The power system of claim 11, further including the first weight factor is equal to one if the relative frequency mismatch is above a first frequency error value, and the first weight factor equal to zero if the relative frequency mismatch is below a second frequency error value. 13. The power system of claim 12, wherein the first frequency error value is between five hertz and five-tenths of a hertz, and the second frequency error value is between one hertz and one-tenth of a hertz. 14. The power system of claim 10, further including the total speed bias circuit initiating the total speed bias when the relative frequency mismatch between the frequency of the bus and the frequency of the generator is below a value selected from a range between ten hertz and one hertz. 15. The power system of claim 10, wherein: the frequency speed bias circuit includes a first integrator and a second integrator, the input to the first integrator being a fixed value based on whether the generator instantaneous voltage is positive and the input to the second integrator being a fixed value based on whether the bus instantaneous voltage is positive, whereby the difference between the first integrator and the second integrator outputs, just before reset of the first integrator and second integrator, determines the relative frequency mismatch of the generator and the bus; andthe phase speed bias circuit is configured to apply XOR logic to a logic signal of the generator voltage waveform and a logic signal of the bus voltage waveform and includes both an XOR output immediately after a leading edge occurrence of the logic signal of the bus voltage waveform, and a logic signal of the bus voltage waveform output detector, using an AND logic function block to compare the results to determine if the phase of the generator lags or leads the phase of the bus. 16. The power system of claim 10, further including a signal limiter that restricts the amount of instantaneous change the frequency speed bias can apply to the speed of an engine of the generator, a signal limiter that restricts the amount of instantaneous change the phase speed bias can apply to the speed of an engine of the generator, and a signal limiter to restrict the amount of instantaneous change the total speed bias can apply to the speed of an engine of the generator. 17. The power system of claim 10, wherein the power system includes a synchronization and load sharing control with a plurality of control devices, each control device being associated with one or more of the plurality of generators and each control device configured to control one or more generators. 18. A power system, comprising: a bus;a plurality of generator sets operable to supply electricity to an electric power load;a generator set including at least a generator and an engine;a synchronization and load sharing control, comprising: a frequency speed bias circuit, including a bandpass filter, a hard limiter, an integrator which resets on leading edge, a hold block, a summer, a first weight factor multiplier, and a first PID controller, the frequency speed bias circuit outputting a frequency speed bias;a phase speed bias circuit, including a bandpass filter, a hard limiter, an integrator which resets on leading edge, a first logic function block, a hold block, a leading edge detector, a second logic function block, a second weight factor multiplier, and a second PID controller, the phase speed bias circuit outputting a phase speed bias;a total speed bias circuit, including a summer and a limiter, the total speed bias circuit outputting a total speed bias; anda generator breaker to connect the generator set to the bus when the voltage, frequency, and phase of the generator set are within a permissible range of the voltage, frequency, and phase of the bus. 19. The power system of claim 18, wherein: the first weight factor is a value between one and zero;the second weight factor also is a value between one and zero;if the first weight factor increases, the second weight factor may decrease and if the first weight factor decreases, the second weight factor may increase;the first weight factor is equal to one if the relative frequency mismatch is above a first frequency error value;the first frequency error value is between five hertz and five-tenths of a hertz;the first weight factor is equal to zero if the relative frequency mismatch is below a second frequency error value;the second frequency error value is between one hertz and one-tenth of a hertz; andthe total speed bias circuit initiating the total speed bias when the relative frequency mismatch between the frequency of the bus and the frequency of the generator is below a value selected from a range between ten hertz and one hertz. 20. The power system of claim 19, wherein the synchronization and load sharing control has a plurality of frequency speed bias circuits, phase speed bias circuits, and total speed bias circuits.
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