IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0397444
(2009-03-04)
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등록번호 |
US-8217706
(2012-07-10)
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발명자
/ 주소 |
- Ball, Alan R.
- Robb, Stephen P.
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출원인 / 주소 |
- Semiconductor Components Industries, LLC
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
8 |
초록
▼
A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion o
A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including a corresponding power FET. When the temperature of the semiconductor substrate near one or more of the power FETs reaches a predetermined value, the corresponding temperature sensing circuit reduces a voltage appearing on the gate of the power FET. The reduced voltage increases the on-resistance of the power FET and channels a portion of its current to others of the plurality of power FETs. The power FET continues operating but with a reduced current flow. When the temperature of the semiconductor substrate falls below the predetermined value, the gate voltage of the power FET is increased to its nominal value.
대표청구항
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1. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device; andreducing a current flowing in the first semiconductor device from a first level to a second level in response to the temperature sensed in th
1. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device; andreducing a current flowing in the first semiconductor device from a first level to a second level in response to the temperature sensed in the portion of the first semiconductor device reaching a predetermined value, wherein in response to reducing the current flowing in the first semiconductor device a current flowing in a second semiconductor device increases, and wherein the first and second semiconductor devices each have first and second current carrying terminals, the first current carrying terminals of the first and second semiconductor devices commonly coupled together and the second current carrying terminals of the first and second semiconductor devices commonly coupled together. 2. The method of claim 1, wherein reducing the current flowing in the first semiconductor device includes reducing a gate voltage of the first semiconductor device. 3. The method of claim 1, further including using a thermal limit circuit having a thermal sense element to sense the temperature. 4. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device; andreducing a current flowing in the first semiconductor device from a first level to a second level in response to the temperature sensed in the portion of the first semiconductor device reaching a predetermined value, wherein reducing the current flowing in the first semiconductor device increases a current flowing in a second semiconductor device, wherein the first and second semiconductor devices each have first and second current carrying terminals, the first current carrying terminals of the first and second semiconductor devices commonly coupled together and the second current carrying terminals of the first and second semiconductor devices commonly coupled together. 5. The method of claim 4, wherein reducing the current flowing in the first semiconductor device includes reducing the conductance of the first semiconductor device. 6. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device; andreducing a current flowing in the first semiconductor device from a first level to a second level when the temperature sensed in the portion of the first semiconductor device reaches a predetermined value, wherein reducing the current flowing in the first semiconductor device includes sharing the current among a plurality of semiconductor devices, and wherein at least one of the semiconductor devices of the plurality of semiconductor devices and the first semiconductor device each have first and second current carrying electrodes, the first current carrying terminal of the first semiconductor device and the first current carrying terminal of the at least one semiconductor device commonly coupled together and the second current carrying electrode of the first semiconductor device and the second current carrying electrode of the at least one semiconductor device of the plurality of semiconductor devices commonly coupled together. 7. The method of claim 6, further including using a thermal limit circuit having a thermal sense element to sense the temperature. 8. A method for protecting a semiconductor chip from thermally induced damage, comprising: sensing a temperature in a portion of the semiconductor chip; andselecting an operating mode for the semiconductor chip using an external pin, wherein the operating mode is selected from the group of operating modes comprising latching a first semiconductor device into an off-state, latching the first semiconductor device into an off-state after a delay, and reducing a current flowing in the first semiconductor device from a first level to a second level. 9. The method of claim 8, wherein reducing the current flowing in the first semiconductor device comprises sharing the current between a plurality of semiconductor devices formed from the semiconductor chip. 10. The method of claim 8, further including providing a plurality of semiconductor devices coupled in parallel wherein the first semiconductor device is a semiconductor device of the plurality of semiconductor devices and wherein reducing the current flowing in the first semiconductor device includes reducing the current flowing in the first semiconductor device independently of other semiconductor devices of the plurality of semiconductor devices. 11. The method of claim 8, further including providing a plurality of semiconductor devices coupled in parallel wherein the first semiconductor device is a semiconductor device of the plurality of semiconductor devices and wherein reducing the current flowing in the first semiconductor device includes maintaining a substantially constant power dissipation from the first semiconductor device. 12. The method of claim 8, further including providing a plurality of semiconductor devices coupled in parallel, wherein the first semiconductor device is a semiconductor device of the plurality of semiconductor devices and wherein the current flowing in each of the plurality of semiconductor devices is at a first level, and wherein reducing the current flowing in the first semiconductor device includes reducing the current flowing in the first semiconductor device of the plurality of semiconductor devices to a second level while maintaining the first semiconductor device in an active operational mode, and further including increasing the current flowing in the first semiconductor device to substantially the first level when the temperature falls below a predetermined level. 13. A method for protecting an integrated circuit from thermally induced damage, comprising: sensing a temperature in a portion of the integrated circuit; andin response to the temperature sensed, operating the integrated circuit in an operating mode selected from the group of operating modes comprising latching a semiconductor device into an off state, latching the semiconductor device into the off-state after a predetermined delay, and operating the integrated circuit with a reduced current flowing in a portion of the integrated circuit to maintain the temperature of the portion of the integrated circuit substantially at or below a predetermined level. 14. The method of claim 13, wherein latching the semiconductor device into the off-state includes using a Resistance-Capacitance (RC) time constant to set the predetermined delay. 15. The method of claim 13, further including using a thermal limit circuit having a thermal sense element to sense the temperature. 16. The method of claim 15, further including operating the thermal limit circuit at a substantially constant temperature when that temperature is reached. 17. The method of claim 13, wherein operating in the operating mode of operating the integrated circuit with the reduced current flowing in the portion of the integrated circuit to maintain the temperature of the portion of the integrated circuit substantially at or below the predetermined level further includes reducing the current flowing in the integrated circuit from a first level to a second level when the temperature sensed in the portion of the integrated circuit reaches a predetermined value. 18. The method of claim 13, further including increasing another current flowing in another portion of the integrated circuit. 19. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device using a thermal limit circuit;reducing a current flowing in the first semiconductor device from a first level to a second level and increasing a current flowing in a second semiconductor device in response to the temperature sensed in the portion of the first semiconductor device reaching a predetermined value, wherein the first and second semiconductor devices are coupled in a parallel configuration; andoperating the thermal limit circuit at a substantially constant temperature when that temperature is reached. 20. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device using a thermal limit circuit having a thermal sense element; andreducing a current flowing in the first semiconductor device from a first level to a second level in response to the temperature sensed in the portion of the first semiconductor device reaching a predetermined value, wherein in response to reducing the current flowing in the first semiconductor device a current flowing in a second semiconductor device increases, and wherein the first and second semiconductor devices are coupled in a parallel configuration; and further including operating the thermal limit circuit at a substantially constant temperature when that temperature is reached. 21. A method for regulating temperature in a first semiconductor device, comprising: sensing temperature in a substrate near the first semiconductor device using a thermal limit circuit having a thermal sense element;reducing a current flowing in the first semiconductor device from a first level to a second level when the temperature sensed in the portion of the first semiconductor device reaches a predetermined value, wherein reducing the current flowing in the first semiconductor device includes sharing the current among a plurality of semiconductor devices; and further including operating the thermal limit circuit at a substantially constant temperature when that temperature is reached.
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