IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0861970
(2010-08-24)
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등록번호 |
US-8217815
(2012-07-10)
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발명자
/ 주소 |
- Chen, Jianqiu
- Smith, Sterling
- Cheng, Jianping
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출원인 / 주소 |
- MStar Semiconductor, Inc.
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대리인 / 주소 |
Edell, Shapiro & Finnan, LLC
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인용정보 |
피인용 횟수 :
5 인용 특허 :
11 |
초록
▼
A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting sig
A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.
대표청구항
▼
1. A multi-path Σ-Δ modulator, comprising: a first integrator, coupled to a first path input end;a second integrator, coupled to a second path input end;a shared operational amplifier (op-amp), being alternately coupled to the first integrator and the second integrator to generate an integrated sign
1. A multi-path Σ-Δ modulator, comprising: a first integrator, coupled to a first path input end;a second integrator, coupled to a second path input end;a shared operational amplifier (op-amp), being alternately coupled to the first integrator and the second integrator to generate an integrated signal;two quantizers, respectively coupled to the first integrator and the second integrator, for comparing the integrated signal with a predetermined signal to output a digital signal;two digital-to-analog converters (DAC), respectively coupled between output ends of the quantizers and the first integrator and the second integrator, for converting the digital signal outputted by the quantizers into an analog signal that is fed to either the first integrator or the second integrator; anda clock signal generator, coupled to the first and second integrators and the quantizers, for providing clock signals for controlling the first and second integrators and the quantizers,wherein the shared op-amp comprises a negative input end, a positive input end and an output end, and the first integrator comprises:a first sampling component, coupled to the first path input end during a first period of a clock cycle and coupled to the negative input end of the shared op-amp during a second period of the clock cycle; anda first integrating component, coupled between the negative input end and the output end of the shared op-amp during the second period of the clock cycle;the second integrator comprises:a second sampling component, coupled to the second path input end during the second period of the clock cycle and coupled to the negative input end of the shared op-amp during the first period of the clock cycle; anda second integrating component, coupled between the negative input end of the output end of the shared op-amp during the first period of the clock cycle;wherein, the clock cycle is determined by the clock signal generator. 2. The modulator as claimed in claim 1, further comprising: a first switch, coupled between the negative input end of the shared op-amp and the first integrating component; anda second switch, coupled between the first integrating component and the output end of the shared op-amp;wherein, the first switch and the second switch are simultaneously closed, and the first switch is opened before the second switch is opened. 3. The modulator as claimed in claim 2, further comprising: a third switch, coupled between the negative input end of the shared op-amp and the second integrating component; anda fourth switch, coupled between the second integrating component and the output end of the shared op-amp;wherein, the third switch and the fourth switch are simultaneously closed, and the third switch is opened before the fourth switch is opened. 4. The modulator as claimed in claim 2, wherein the first switch is a T-type switch. 5. The modulator as claimed in claim 1, wherein the clock signals generated by the clock signal generator comprise two non-overlapped clock signals. 6. A multi-path Σ-Δ modulator, comprising: a first integrator, coupled to a first path input end;a second integrator, coupled to a second path input end;a first shared op-amp, being alternately coupled to the first integrator and the second integrator to generate a first integrated signal;a third integrator, coupled to the first path input end and the first shared op-amp;a fourth integrator, coupled to the second path input end and the first shared op-amp;a second shared op-amp, being alternately coupled to the third integrator and the fourth integrator to generate a second integrated signal according to the first integrated signal,two quantizers, respectively coupled to the third integrator and the fourth integrator, for comparing the second integrated signal with a predetermined signal to output a digital signal;two DACs, respectively coupled between output ends of the two quantizers and the first integrator, the second integrator, the third integrator and the fourth integrator, for converting the digital signal outputted by the quantizers to an analog signal that is fed to either the first integrator and the third integrator or the second integrator and the fourth integrator; anda clock signal generator, coupled to the first integrator, the second integrator, the third integrator, the fourth integrator and the quantizers, for providing clock signals for controlling the first integrator, the second integrator, the third integrator, the fourth integrator and the quantizers. 7. The modulator as claimed in claim 6, wherein the first shared op-amp comprises a negative input end, a positive input end and an output end, and the first integrator comprises: a first sampling component, coupled to the first path input end during a non-second period of a clock cycle and coupled to the negative input end of the first shared op-amp during a second period of the clock cycle; anda first integrating component, coupled between the negative input end and the output end of the first shared op-amp during the second period of the clock cycle;the second integrator comprises:a second sampling component, coupled to the second path input end during a non-first period of the clock cycle and coupled to the negative input end of the first shared op-amp during a first period of the clock cycle; anda second integrating component, coupled between the negative input end and the output end of the first shared op-amp during the first period of the clock cycle;wherein, the clock cycle is determined by the clock signal generator. 8. The modulator as claimed in claim 7, wherein the second shared op-amp comprises a negative input end, a positive input end and an output end, and the third integrator comprises: a third integrating component, coupled between the negative input end and the output end of the second shared op-amp during the first period of the clock cycle;a third sampling component, coupled to the negative input end of the second shared op-amp during the first period of the clock cycle, and coupled to the first path input end during a previous period of the first period of the clock cycle; anda fourth sampling component, coupled to the first integrating circuit during the first period of the clock cycle, and coupled to the negative input end of the second shared op-amp during the previous period of the first period of the clock cycle;the fourth integrator comprises:a fourth integrating component, coupled between the negative input end and the output end of the second shared op-amp during the second period of the clock cycle;a fifth sampling component, coupled to the negative input end of the second shared op-amp during the second period of the clock cycle, and coupled to the second path input end during a previous period of the second period of the clock cycle; anda sixth sampling component, coupled to the first integrating circuit during the second period of the clock cycle, and coupled to the negative input end of the second shared op-amp during the previous period of the second period of the clock cycle. 9. The modulator as claimed in claim 8, further comprising: a first plurality of switches, coupled between negative input ends of the first and second shared op-amps and the integrating components; anda second plurality of switches, coupled between the integrating components and output ends of the first and second shared op-amps;wherein, the first plurality of switches and the second plurality of switches are simultaneously closed, and the first plurality of switches are opened before the second plurality of switches are opened. 10. The modulator as claimed in claim 9, wherein the first plurality of switches are T-type switches. 11. The modulator as claimed in claim 8, further comprising: a third plurality of switches, coupled between the negative input ends of the first and second op-amps and the sampling components; anda fourth plurality of switches, coupled between the output ends of the first and second op-amps and the sampling components of the third integrator and the fourth integrator;wherein, the third plurality of switches are opened before the fourth plurality of switches are opened. 12. The modulator as claimed in claim 6, wherein the clock signals generated by the clock signal generator comprise two non-overlapped clock signals. 13. The modulator as claimed in claim 6, further comprising a feed-forward gain unit, coupled between the first integrator and the third integrator and between the third integrator and the fourth integrator, for increasing a feed-forward gain factor to restrain signal components of the first integrated signal outputted by the first shared op-amp, so as to reduce crosstalk between multiple paths. 14. A multi-path Σ-Δ modulating method for a multi-path Σ-Δ modulator with a shared op-amp, the multi-path Σ-Δ modulator being inputted with a first input signal and a second input signal and correspondingly outputting a first output signal and a second output signal, the method comprising: sampling the first input signal during a second period of a clock cycle to obtain a first sampled signal, and integrating the first sampled signal, and a feedback signal of the first output signal during a first period of the clock cycle to obtain a first integrated signal; andsampling the second input signal during a first period of the clock cycle to obtain a second integrated signal, and integrating the second sampled signal and a feedback signal of the second output signal during a second period of the clock cycle to obtain a second integrated signal,the multi-path Σ-Δ modulator outputting a third output signal and a fourth output signal, and the method further comprising:respectively sampling the first input signal and the first integrated signal during the first period of the clock cycle to obtain a third sampled signal and a fourth sampled signal, and integrating the third sampled signal, the fourth sampled signal and a feedback signal of the third output signal during a next period of the first period of the clock cycle to obtain a third integrated signal; andrespectively sampling the second input signal and the second integrated signal during the second period of the clock cycle to obtain a fifth sampled signal and a sixth sampled signal, and integrating the fifth sampled signal, the sixth sampled signal and a feedback signal of the fourth output signal during a next period of the second period of the clock cycle to obtain a fourth integrated signal. 15. The method as claimed in claim 14, wherein the feedback signal of the first output signal is generated by quantizing and digital-to-analog converting the first integrated signal, and the feedback signal of the second output signal is generated by quantizing and digital-to-analog converting the second integrated signal. 16. The method as claimed in claim 14, wherein the feedback signal of the third output signal is generated by quantizing and digital-to-analog converting the third integrated signal, and the feedback signal of the fourth output signal is generated by quantizing and digital-to-analog converting the fourth integrated signal. 17. The method as claimed in claim 14, wherein the clock cycle is determined by two non-overlapped clock signals generated by a clock signal generator. 18. The method as claimed in claim 17, wherein the two non-overlapped clock signals comprise a delayed clock signal and an original clock signal.
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