$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0750364 (2010-03-30)
등록번호 US-8222139 (2012-07-17)
발명자 / 주소
  • Chen, Ming-Fa
  • Lin, I-Ching
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Lowe Hauptman Ham & Berner, LLP
인용정보 피인용 횟수 : 5  인용 특허 : 35

초록

A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a conta

대표청구항

1. A method of forming a through-silicon via (TSV) structure, comprising: providing a semiconductor substrate having a first region and a second region;forming a dielectric layer on the semiconductor substrate, wherein the dielectric layer comprises a first opening in the first region;forming a firs

이 특허에 인용된 특허 (35)

  1. Chen,Chien Hua; Chen,Zhizhang; Meyer,Neal W., 3D interconnect with protruding contacts.
  2. Matsui,Satoshi, Chip and multi-chip semiconductor device using thereof and method for manufacturing same.
  3. Pogge, H. Bernhard; Yu, Roy; Prasad, Chandrika; Narayan, Chandrasekhar, Chip and wafer integration process using vertical connections.
  4. Chanchani,Rajen, Heterogeneously integrated microsystem-on-a-chip.
  5. Chudzik, Michael Patrick; Dennard, Robert H.; Divakaruni, Rama; Furman, Bruce Kenneth; Jammy, Rajarao; Narayan, Chandrasekhar; Purushothaman, Sampath; Shepard, Jr., Joseph F.; Topol, Anna Wanda, High density chip carrier with integrated passive devices.
  6. Chudzik,Michael Patrick; Dennard,Robert H.; Divakaruni,Rama; Furman,Bruce Kenneth; Jammy,Rajarao; Narayan,Chandrasekhar; Purushothaman,Sampath; Shepard, Jr.,Joseph F.; Topol,Anna Wanda, High density chip carrier with integrated passive devices.
  7. Siniaguine, Oleg, Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate.
  8. Siniaguine Oleg, Integrated circuits and methods for their fabrication.
  9. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  10. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  11. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  12. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities.
  13. Tadatomo Suga JP, Interconnect structure for stacked semiconductor device.
  14. Patti, Robert, Interlocking conductor method for bonding wafers to produce stacked integrated circuits.
  15. Matsui,Kuniyasu, Intermediate chip module, semiconductor device, circuit board, and electronic device.
  16. Eilert,Sean S., Method and apparatus for generating a device ID for stacked devices.
  17. Valluri R. Rao ; Jeffrey K. Greason ; Richard H. Livengood, Method for distributing a clock on the silicon backside of an integrated circuit.
  18. Black Charles Thomas ; Burghartz Joachim Norbert ; Tiwari Sandip ; Welser Jeffrey John, Method for making three dimensional circuit integration.
  19. Tadatomo Suga JP, Method for manufacturing an interconnect structure for stacked semiconductor device.
  20. Redwine Donald J. (Houston TX), Method of interconnect in an integrated circuit.
  21. Jackson, Timothy L.; Murphy, Tim E., Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof.
  22. Morrow, Patrick; List, R. Scott; Kim, Sarah E., Methods of forming backside connections on a wafer stack.
  23. Thomas,Jochen; Schoenfeld,Olaf, Multi-chip device and method for producing a multi-chip device.
  24. Farnworth, Warren M.; Wood, Alan G.; Hiatt, William M.; Wark, James M.; Hembree, David R.; Kirby, Kyle K.; Benson, Pete A., Multi-dice chip scale semiconductor components and wafer level methods of fabrication.
  25. Gilmour Richard J. (Liberty Hill TX) Schrottke Gustav (Austin TX), Multiprocessor module packaging.
  26. Siniaguine Oleg ; Savastiouk Sergey, Package of integrated circuits and vertical integration.
  27. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  28. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Packaging substrates for integrated circuits and soldering methods.
  29. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
  30. Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
  31. Jackson, Timothy L.; Murphy, Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies.
  32. Jackson,Timothy L.; Murphy,Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods.
  33. Fey,Kate E.; Byers,Charles L.; Mandell,Lee J., Space-saving packaging of electronic circuits.
  34. Kong, Sik On, Three dimensional IC package module.
  35. Rumer, Christopher L.; Zarbock, Edward A., Through silicon via, folded flex microelectronic package.

이 특허를 인용한 특허 (5)

  1. Lin, Yu-Hung; Lin, Sheng-Hsuan; Chang, Chih-Wei; Chou, You-Hua; Hsu, Chia-Lin, Composite contact plug structure and method of making same.
  2. Lin, Yu-Hung; Lin, Sheng-Hsuan; Chang, Chih-wei; Chou, You-Hua; Hsu, Chia-Lin, Composite contact plug structure and method of making same.
  3. Wang, Chin-Shan; Lee, Shun-Yi, Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer.
  4. Yamashita, Daisuke, Semiconductor apparatus having penetration electrode and method for manufacturing the same.
  5. Chen, Yi-An; Lu, Yung-Jean; Thomas, III, Windsor Pipes, Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로