초록 ▼

Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sam

Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.

대표청구항 ▼

1. An apparatus comprising: a plurality of track-and-hold (T/H) circuits that receive an analog input signal;a multiplexer that is coupled to each of the T/H circuits;an analog-to-digital converter (ADC) that is coupled to the multiplexer;a clocking circuit that receives a clock signal and that is c

1. An apparatus comprising: a plurality of track-and-hold (T/H) circuits that receive an analog input signal;a multiplexer that is coupled to each of the T/H circuits;an analog-to-digital converter (ADC) that is coupled to the multiplexer;a clocking circuit that receives a clock signal and that is coupled to each of the T/H circuits and the multiplexer, wherein the clocking circuit controls the T/H circuits such that tracking phases for the T/H circuits are generally non-overlapping, and wherein the clocking circuit controls the coupling between each T/H circuit and the ADC with the multiplexer;a digital-to-analog converter (DAC) that is coupled to the ADC;an adder that is coupled to the DAC and the multiplexer so as to determine the difference between output signals of the DAC and multiplexer; andan amplifier that is coupled to the adder. 2. The apparatus of claim 1, wherein the clock circuit further comprises a clock divider. 3. An apparatus comprising: a plurality of stages that are coupled in series with one another in a sequence, wherein the first stage of the sequence receives an analog input signal, and wherein each stage outputs a residue signal, and wherein each stage includes: a plurality of T/H circuits that receive the analog input signal or the residue signal from the previous stage;a multiplexer that is coupled to each of the T/H circuits; anda first ADC that is coupled to the multiplexer; anda clocking circuit that receives a clock signal and that is coupled to each of the T/H circuits and the multiplexer, wherein the clocking circuit controls the T/H circuits such that tracking phases for the T/H circuits for each stage are generally non-overlapping, and wherein the clocking circuit controls the coupling between each T/H circuit for each stage and each first ADC with the multiplexer for each stage;a second ADC that is coupled to the last stage of the sequence so as to receive its residue signal; anda digital output circuit that is coupled the each stage and the second ADC so as to generate a digital output signal. 4. The apparatus of claim 3, wherein each stage further comprises: a DAC that is coupled to the first ADC;an adder that is coupled to the DAC and the multiplexer so as to determine the difference between output signals of the DAC and multiplexer; andan amplifier that is coupled to the adder. 5. The apparatus of claim 4, wherein the clock circuit further comprises a clock divider. 6. An apparatus comprising: a plurality of stages that are coupled in series with one another in a sequence, wherein the first stage of the sequence receives an analog input signal, and wherein each stage outputs a residue signal, and wherein each stage includes: a first T/H circuit that receives the analog input signal or the residue signal from the previous stage;a second T/H circuit that receives the analog input signal or the residue signal from the previous stage;a multiplexer that is coupled to the first and second T/H circuits; anda first ADC that is coupled to the multiplexer; anda clocking circuit that receives a clock signal and that is coupled to each of the T/H circuits and the multiplexer, wherein the clocking circuit controls the T/H circuits such that tracking phases for the T/H circuits for each stage are generally non-overlapping, and wherein the clocking circuit controls the coupling between each T/H circuit for each stage and each first ADC with the multiplexer for each stage;a second ADC that is coupled to the last stage of the sequence so as to receive its residue signal; anda digital output circuit that is coupled the each stage and the second ADC so as to generate a digital output signal. 7. The apparatus of claim 6, wherein each stage further comprises: a DAC that is coupled to the first ADC;an adder that is coupled to the DAC and the multiplexer so as to determine the difference between output signals of the DAC and multiplexer; andan amplifier that is coupled to the adder. 8. The apparatus of claim 7, wherein the clock circuit further comprises a clock divider. 9. The apparatus of claim 8, wherein the clock divider is a divide-by-2 clock divider so as to generate a halved clock signal. 10. The apparatus of claim 9, wherein each first T/H circuit is in its track phase when the halved clock signal is in a first logic state and in its hold phase in when the halved clock signal is in a second logic state, and wherein each first T/H circuit is coupled to its first ADC through its multiplexer when the halved clock signal is in the second logic state. 11. The apparatus of claim 10, wherein each second T/H circuit is in its hold phase when the halved clock signal is in the first logic state and in its track phase in when the halved clock signal is in the second logic state, and wherein each second T/H circuit is coupled to its first ADC through its multiplexer when the halved clock signal is in the first logic state. 12. The apparatus of claim 11, wherein the first logic state is logic high, and wherein the second logic state is logic low.