Specialized processing block for programmable logic device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-007/38
H03K-019/173
H03K-019/177
출원번호
US-0447329
(2006-06-05)
등록번호
US-8266198
(2012-09-11)
발명자
/ 주소
Lee, Kwan Yee Martin
Langhammer, Martin
Lin, Yi-Wen
Nguyen, Triet M.
출원인 / 주소
Altera Corporation
대리인 / 주소
Ropes & Gray LLP
인용정보
피인용 횟수 :
8인용 특허 :
291
초록▼
A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit p
A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.
대표청구항▼
1. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each
1. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including:a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product,compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, andcircuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; said specialized processing block further comprising:rounding circuitry that provides both:a first user-selectable option to round said result to a nearest integer, anda second user-selectable option to round said result to a nearest even integer. 2. The specialized processing block of claim 1 wherein said rounding circuitry accepts input of a variable that encodes a bit position at which rounding of said result is performed. 3. The specialized processing block of claim 1 wherein: said arithmetic circuitry operates on values in a range that extends up to a most highly positive value and down to a most highly negative value; said specialized processing block further comprising:saturation circuitry for clipping said result to a value inside said range; wherein:said saturation circuitry accepts input of a variable that encodes a bit position at which saturation of said result is performed. 4. The specialized processing block of claim 3 wherein said saturation circuitry clips said results symmetrically. 5. The specialized processing block of claim 3 wherein said saturation circuitry clips said results asymmetrically. 6. The specialized processing block of claim 3 wherein said saturation circuitry operates after said rounding circuitry. 7. The specialized processing block of claim 1 wherein said rounding circuitry is programmably locatable to optimize operation of said specialized processing block. 8. The specialized processing block of claim 7 wherein at least a first portion of said rounding circuitry is programmably locatable in parallel with at least a portion of said arithmetic circuitry to operate in a look-ahead mode. 9. The specialized processing block of claim 8 wherein: said portion of said arithmetic circuitry computes said result without rounding;said first portion of said rounding circuitry computes said result with rounding in parallel with computation by said portion of said arithmetic circuitry of said result without rounding; andsaid rounding circuitry further comprises a second portion that selects between said result with rounding and said result without rounding. 10. The specialized processing block of claim 7 wherein: said arithmetic circuitry includes a register creating a critical timing path; andsaid rounding circuitry is programmably locatable in at least one position that is at least one of (a) before, and (b) after, said register so as to be programmably includable in, and excludable from, said critical timing path. 11. The specialized processing block of claim 10 wherein said critical timing path includes results chained from another said specialized processing block. 12. A programmable logic device comprising the specialized processing block of claim 1. 13. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable logic device as defined in claim 12 coupled to the processing circuitry and the memory. 14. A printed circuit board on which is mounted a programmable logic device as defined in claim 12. 15. The printed circuit board defined in claim 14 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device. 16. The printed circuit board defined in claim 15 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 17. An integrated circuit device comprising the specialized processing block of claim 1. 18. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 17 coupled to the processing circuitry and the memory. 19. A printed circuit board on which is mounted an integrated circuit device as defined in claim 18. 20. The printed circuit board defined in claim 19 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device. 21. The printed circuit board defined in claim 20 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 22. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry that operates on values in a range that extends up to a most highly positive value and down to a most highly negative value for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including:a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product,compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, andcircuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; said specialized processing block further comprising:saturation circuitry for clipping said result to a value inside said range; wherein:said saturation circuitry accepts input of a variable that encodes a bit position at which saturation of said result is performed. 23. The specialized processing block of claim 22 wherein said saturation circuitry clips said results symmetrically. 24. The specialized processing block of claim 22 wherein said saturation circuitry clips said results asymmetrically. 25. A programmable logic device comprising the specialized processing block of claim 22. 26. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable logic device as defined in claim 25 coupled to the processing circuitry and the memory. 27. A printed circuit board on which is mounted a programmable logic device as defined in claim 25. 28. The printed circuit board defined in claim 27 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device. 29. The printed circuit board defined in claim 28 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 30. An integrated circuit device comprising the specialized processing block of claim 22. 31. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 30 coupled to the processing circuitry and the memory. 32. A printed circuit board on which is mounted an integrated circuit device as defined in claim 31. 33. The printed circuit board defined in claim 32 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device. 34. The printed circuit board defined in claim 33 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (291)
Hogenauer, Eugene B., Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks.
Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
Jekel Richard N. (La Mesa CA), Apparatus and method for combining analog and digital automatic gain control in receivers with digital signal processing.
Cho, Won-kyoung; Kim, Jung-wook; Park, In-cheol; Lee, Eul-hwan; Kang, Hyeong-ju, Apparatus and method of multiplication using a plurality of identical partial multiplication modules.
Doddington George D. (McLean VA) Pawate Basavaraj (Dallas TX) Mahant-Shetti Shivaling (Richardson TX) Smith Derek (Lafayette LA), Apparatus, system and methods for distributed signal processing.
Pawate Basavaraj (Dallas TX) Doddington George (McLean VA) Mahant-Shetti Shivaling S. (Richardson TX) Smith Derek (Lafayette LA), Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit.
Balmer Keith (Bedford GB2) Ing-Simmons Nicholas (Huntingdon GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX) Read Christopher J. (Houston TX) Polan, Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section.
Yu, Robert K.; Padmanabhan, Satish; Srivatsa, Chakra R.; Shah, Shailesh I., Circuit and method for multiplying and accumulating the sum of two products in a single cycle.
Reddy Srinivas T. ; Zaveri Ketan ; Lane Christopher F. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B. ; Mejia Manuel ; Cliff Richard G., Circuitry and methods for internal interconnection of programmable logic devices.
Gomola John W. (Pittsburgh PA) Wood William G. (Pittsburgh PA) Jones F. David (Pittsburgh PA) Wallace Frank E. (Irwin PA) Marano Ross T. (Murrysville PA), Combined file and directory system for a process control digital computer system.
Phillips William C. ; Pascale Michael V. ; Minarik Ronald W. ; Schmidt Kenneth M. ; Weigand Benjamin F. ; Dirndorfer Walter M. ; Prill Robert S. ; Siegel Arnold B. ; Nogay Richard H., Common receive module for a programmable digital radio.
Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
Ramamurthy Srinivas ; Berger Neal ; Fahey ; Jr. James,FRX ; Gongwer Geoffrey S. ; Saiki William J. ; Tam Eugene Jinglun, Configuration control in a programmable logic device using non-volatile elements.
Weng Chia-Shiann (Austin TX) Kuenast Walter U. (Austin TX) Anderson Donald C. (Austin TX) Curtis Peter C. (Austin TX) Greene Richard L. (Austin TX), DSP co-processor for use on an integrated circuit that performs multiple communication tasks.
Ehlig Peter N. (Houston TX) Boutaud Frederic (Roquefort les Pins FRX) Hollander James F. (Dallas TX), Data processor with sets of two registers where both registers receive identical information and when context changes in.
Taborn Michael Preston (Austin TX) Burchfiel Steven Michael (Austin TX) Matheny David Terrence (Austin TX), Denormalization system and method of operation.
Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Furtek Frederick (Menlo Park CA), Diagonal wiring between abutting logic cells in a configurable logic array.
Gomola John W. (Pittsburgh PA) Giras Theodore C. (Pittsburgh PA) Wood William G. (Pittsburgh PA) Putman Richard E. (Pittsburgh PA) Gilbreath Rodney E. (Pittsburgh PA) Deliyannides John S. (Wilmington, Digital computer monitored and/or operated system or process which is structured for operation with an improved automati.
Brueckmann Dieter (Meerbusch DEX) Preuss Walfried (Hoehenkirchen-Siegertsb DEX), Digital signal processing device with optimized ALU circuit and logic block for controlling one of two registers based o.
Adrian Andrew A. (Melrose MA) Danielson Michael S. (Wrentham MA) Meyers David B. (Walpole MA) Spiegel Leo (Sharon MA), Digital signal processing for linearization of small input signals to a tri-state power switch.
Phillips William C. ; Hilterbrick Charles L. ; Minarik Ronald W. ; Schmidt Kenneth M. ; Pascale Michael V. ; Prill Robert S., Digitally programmable multifunction radio system architecture.
Brown Elliott, Candice Hellen; Higgins, Michael Francis; Han, Seok Jin; Credelle, Thomas Lloyd, Display system having improved multiple modes for displaying image data from multiple input source formats.
Hailey Keith R. (Amershan Buckinghamshire GB2) Storey John J. (Hertfordshire GB2), Dual-mode image interpolation filter operable in a first mode for storing interpolation coefficients and in a second mod.
Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel ; Cliff Richard G. ; Veenstra Kerry, Dual-port programmable logic device variable depth and width memory array.
McGowan John E. ; Plants William C. ; Landry Joel D. ; Kaptanoglu Sinan ; Miller Warren K., Flexible, high-performance static RAM architecture for field-programmable gate arrays.
Lloyd C. Cox ; Gary A. Gramlich ; Robert M. Baker ; Stephen Freeman ; Brian P. Neary ; Cynthia R. Krzemien ; Jordan A. Krim ; Luis R. Nunez, General purpose filter.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valerity B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ;, Hexagonal sense cell architecture.
Ku Walter H. (La Jolla CA) Linderman Richard W. (Dayton OH) Chau Paul M. (Ithaca NY) Reusens Peter P. (Destel Bergin BEX), High performance signal processor.
Boland, Liza G.; Janssen, Johan G., Image interpolation and decimation using a continuously variable delay filter and combined with a polyphase filter.
Pierce Kerry M. ; Erickson Charles R. ; Huang Chih-Tsung ; Wieland Douglas P., Interconnect architecture for field programmable gate array using variable length conductors.
Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.
Hsieh ; deceased Hung-Cheng (late of Sunnyvale CA) Carter ; administrator by William S. (Santa Clara CA) Erickson Charles R. (Fremont CA) Cheung Edmond Y. (San Jose CA), Logic structure and circuit for fast carry.
Hsieh Hung-Cheng (583 Loch Lomond Ct. Sunnyvale CA 94087) Carter William S. (3024 Aspen Dr. Santa Clara CA 95051) Erickson Charles S. (3412 Atwater Ct. Fremont CA 94536) Cheung Edmond Y. (1302 Shelby, Logic structure and circuit for fast carry.
Tobias David F., Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic.
Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Logic system of logic networks with programmable selected functions and programmable operational controls.
Yatim David (Austin TX) Girardeau ; Jr. James W. (Austin TX), Method and apparatus for a multiply and accumulate circuit having a dynamic saturation range.
Keller, Eric R.; Patterson, Cameron D., Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices.
Harrison David A. (Cupertino CA) Silver Joshua M. (Sunnyvale CA) Soe Soren T. (San Jose CA), Method for programming complex PLD having more than one function block type.
Farrugia, Jennifer; Ahmed, Elias; Bourgeault, Mark, Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions.
Hennedy,Michael; Friedman,Vladimir; Speziale,Artemas; Sherkat,Mohammad Reza, Micro-programmable filter engine having plurality of filter elements interconnected in chain configuration wherein engine supports multiple filters from filter elements.
Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Kolze Paige A. ; Chan Andrew K. ; Apland James A., Programmable integrated circuit having a test circuit for testing the integrity of routing resource structures.
Pass Christopher J. ; Sansbury James D. ; Madurawe Raminda U. ; Turner John E. ; Patel Rakesh H. ; Wright Peter J., Programmable interconnect junction.
Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.
Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
Boggs, Mark Steven; Fulton, Temple L.; Hausman, Steve; McNabb, Gary; McNutt, Alan; Stimmel, Steven W., Programmable logic controller customized function call method, system and apparatus.
Boggs, Mark Steven; Fulton, Temple L.; Hausman, Steve; McNabb, Gary; McNutt, Alan; Stimmel, Steven W., Programmable logic controller method, system and apparatus.
Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.
Lane Christopher F. ; Reddy Srinivas T. ; Cliff Richard G. ; Zaveri Ketan H. ; Pedersen Bruce B. ; Veenstra Kerry, Programmable logic device circuitry for improving multiplier speed and/or efficiency.
Pedersen Bruce B. ; Shumarayev Sergey ; Huang Wei-Jen ; Chan Vinson ; Brown Stephen,CAX ; Ngai Tony ; Park James, Programmable logic device configured to accommodate multiplication.
Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.
Patel Rakesh H. (Santa Clara CA) Turner John E. (Santa Cruz CA) Wong Myron W. (San Jose CA), Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnec.
Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
Zaveri Ketan ; Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B., Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.
Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA), Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers.
Khong James C. K. (San Jose CA) Mueller Wendey E. (Fremont CA) Yu Joe (Palo Alto CA) Berger Neal (Cupertino CA) Gudger Keith H. (Soquel CA) Gongwer Geoffrey S. (Campbell CA), Programmable logic device with regional and universal signal routing.
Ozawa,Kunihiko, Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system.
Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., System for distributing clocks using a delay lock loop in a programmable logic circuit.
Guttag Karl M. (Missouri City TX) Simpson Richard (Bedford GB2) Walsh Brendan (Bedford GB2), Three input arithmetic logic unit forming mixed arithmetic and boolean combinations.
Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with barrel rotator and mask generator.
Guttag Karl M. (Missouri City TX) Balmer Keith (Bedford GB2) Gove Robert J. (Plano TX) Read Christopher J. (Houston TX) Golston Jeremiah E. (Sugar Land TX) Poland Sydney W. (Katy TX) Ing-Simmons Nich, Three input arithmetic logic unit with mask generator.
Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Phillip,GBX, Three input arithmetic logic unit with shifter.
Guttag Karl M. ; Balmer Keith,GBX ; Gove Robert J. ; Read Christopher J. ; Golston Jeremiah E. ; Poland Sydney W. ; Ing-Simmons Nicholas,GBX ; Moyse Philip,GBX, Three input arithmetic logic unit with shifter and/or mask generator.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
Langhammer, Martin, Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.