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Extension of swing modulo scheduling to evenly distribute uniform strongly connected components 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0233895 (2008-09-19)
등록번호 US-8266610 (2012-09-11)
발명자 / 주소
  • Martin, Allan Russell
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Yee & Associates, P.C.
인용정보 피인용 횟수 : 1  인용 특허 : 38

초록

A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series of instructions. Schedule execution

대표청구항

1. A method in a data processing system for scheduling instructions for execution, the method comprising: identifying a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency;determining whether the series of instructions is a uniform series of instructions

이 특허에 인용된 특허 (38)

  1. Muthukumar, Kalyan; Helder, David A, Compare speculation in software-pipelined loops.
  2. Srinivasan, Uma; Nomura, Kevin; Ju, Dz-ching, Data speculation within modulo scheduled loops.
  3. Martin,Allan Russell, Extension of swing modulo scheduling to evenly distribute uniform strongly connected components.
  4. Goebel Kurt J., Functional unit switching for the allocation of registers.
  5. Partha Pal Tirumalai ; Rajagopalan Mahadevan, Integration of data prefetching and modulo scheduling using postpass prefetch insertion.
  6. Tirumalai, Partha Pal; Mahadevan, Rajagopalan, Integration of data prefetching and modulo scheduling using postpass prefetch insertion.
  7. Ruttenberg John C. (Waban MA), Loop scheduler.
  8. Muthukumar, Kalyan; Doshi, Gautam B., Mechanism for software pipelining loop nests.
  9. Helder, David A; Muthukumar, Kalyan, Mechanism to avoid explicit prologs in software pipelined do-while loops.
  10. Tirumalai Partha P. (Fremont CA), Method and apparatus for automatic selection of the load latency to be used in modulo scheduling in an optimizing compil.
  11. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  12. Thompson,Carol L.; Srinivasan,Uma; Hank,Richard E.; Morris,Dale, Method and apparatus for efficient code generation for modulo scheduled uncounted loops.
  13. Tirumalai Partha P., Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler.
  14. Tirumalai Partha P. ; Subramanian Krishna ; Baylin Boris, Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions.
  15. Kumar,Anoop; Nair,Sreekumar Ramakrishnan, Method and apparatus for integrated instruction scheduling and register allocation in a postoptimizer.
  16. Hwu,Wen mei W.; Merten,Matthew C., Method and apparatus for modulo scheduled loop execution in a processor architecture.
  17. Rajagopalan,Mahadevan, Method and apparatus for multi-versioning loops to facilitate modulo scheduling.
  18. Rozas, Guillermo J., Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations.
  19. Subramanian Krishna ; Baylin Boris, Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler.
  20. Stringer,Lynd M., Method and system for scheduling software pipelined loops.
  21. Granston, Elana D.; Zbiciak, Joseph; Ward, Alan S.; Stotzer, Eric J., Method for collapsing the prolog and epilog of software pipelined loops.
  22. Bonaventure,Damien; McInnes,James Lawrence, Method for minimizing spill in code scheduled by a list scheduler.
  23. Rasbold James C. (Livermore CA) Van Dyke Don A. (Pleasanton CA), Method for optimizing instruction scheduling for a processor having multiple functional resources.
  24. Bharadwaj,Jayashankar; Shpeisman,Tatiana; Adl Tabatabai,Ali Reza, Method for register allocation during instruction scheduling.
  25. Granston, Elana D.; Zbiciak, Joseph; Stotzer, Eric J., Method for software pipelining of irregular conditional control loops.
  26. Gupta Rajiv (Ossining NY), Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data depe.
  27. Sivaraman,Mukund; Gupta,Shail Aditya, Method of using clock cycle-time in determining loop schedules during circuit design.
  28. Srinivasan, Uma, Method, apparatus, and product for optimizing compiler with rotating register assignment to modulo scheduled code in SSA form.
  29. Bliss, Brian E., Modulo scheduling via binary search for minimum acceptable initiation interval method and apparatus.
  30. Hsu Wei ; Staley Loren, Optimizing compiler having data cache prefetch spreading.
  31. Martin,Allan Russell, Pinning internal slack nodes to improve instruction scheduling.
  32. Swoboda, Gary L., Pipeline flattener for simplifying event detection during data processor debug operations.
  33. Ostanevich, Alexander Y.; Volkonsky, Vladimir Y., Register economy heuristic for a cycle driven multiple issue instruction scheduler.
  34. Muthukumar, Kalyan; Lavery, Daniel M.; Hoflehner, Gerolf F.; Lim, Chu cheow; Collard, Jean Francois, Resource-aware scheduling for compilers.
  35. Martin,Allan Russell; McInnes,James Lawrence, Scheduling technique for software pipelining.
  36. Chan Sun C. (Fremont CA) Dehnert James C. (Palo Alto CA) Lo Raymond W. (Sunnyvale CA) Towle Ross A. (San Francisco CA), System and method of generating object code using aggregate instruction movement.
  37. Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for loop instruction scheduling hardware lookahead.
  38. Ju Dz-Ching, Unified compiler framework for control and data speculation with recovery code.

이 특허를 인용한 특허 (1)

  1. Ahn, Min-wook; Kim, Won-sub; Jin, Tai Song; Lee, Seung-won; Lee, Jin-seok; Im, Chae-seok, Method and apparatus of instruction scheduling using software pipelining.
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