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The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller ca

The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter.

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1. A control core configured to implement a control key equation to produce a plurality of drive signals for a three-phase two or three-level converter, having a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; wherein a vol

1. A control core configured to implement a control key equation to produce a plurality of drive signals for a three-phase two or three-level converter, having a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; wherein a voltage signal Vm is used to multiply a sawtooth or triangular signal to form a scalable sawtooth or triangular signal; andthe sawtooth or triangular signal is input into two comparators to compare with two output signals from a signal adjustment unit, resulting in trailing edge, leading edge, or double edge signals Qp and Qn. 2. The control core in claim 1, wherein: a combination of selected line current signals and reference signals are inputs to the signal adjustment unit;a constant value is integrated by an integrator and then added to itself by an adder (subtractor);an output from the adder (subtractor) is multiplied by the voltage signal Vm and is compared with two output signals from the signal adjustment unit using the two comparators;two flip-flops are set by an arrival of a clock signal and reset by a change of state of output signals of the comparators, resulting in drive signals Qp and Qn; andthe integrator is reset any time after the flip-flops are reset and before the end of a next switching cycle. 3. The control core in claim 1, wherein: a combination of selected line current signals and reference signals are inputs to the signal adjustment unit;a voltage signal Vm is integrated by an integrator and then added to itself by an adder (subtractor);an output signal from the adder (subtractor) is compared to the two output signals from the signal adjustment unit;two flip-flops are set by an arrival of a clock signal and reset by a change of state of output signals from the comparators, resulting in drive signals Qp and Qn; andthe integrator is reset any time after the flip-flops are reset and before the end of a next switching cycle. 4. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising: a first and a second pulse-width modulator; anda reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein;the first and second pulse-width modulators are each based on comparing a signal with a saw-tooth or triangle waveform;two vector voltage signals, vp and vn, and two current signals, ip and in, are selected for each operating region;the two current signals ip and in are input to two input terminals of a first signal adjustment unit;the two voltage signals vp and vn are input to two multipliers respectively and each is multiplied by a voltage signal Vm to form two scalable voltage signals (Vp*Vm) and (Vn*Vm);the two scalable voltage signals (Vp*Vm) and (Vn*Vm) are input into two input terminals of a second signal adjustment unit;output signals of the first and second signal adjustment units are combined by two adders (subtractors) respectively;output signals from the two adders (subtractors) are compensated by two compensators respectively to produce two compensated output signals, each compensator having a function Gc(s); andthe two compensated output signals are compared with a sawtooth or triangular signal in order to produce leading edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Qp and Qn. 5. The control core in claim 4, wherein the first and the second pulse width modulators are each based on an integrator with reset. 6. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising: a first and a second pulse-width modulator; anda reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein:two vector voltage signals, vp and vn, and two current signals, ip and in, are selected for each operating region;the two voltage signals vp and vr, are input to two multipliers and each is multiplied by a voltage signal Vm to form scalable voltage signals (Vp*Vm) and (Vn*Vm);the two scalable voltage signals (Vp*Vm) and (Vn*Vm) and the two current signals ip and in are combined by two adders (subtractors);output signals from the two adders (subtractors) are then input into two input terminals of a signal adjustment unit;two output signals from the signal adjustment unit are compensated by a compensator having a function Gc(s) to produce two compensated signals; andthe two compensated signals are compared with a sawtooth or triangular signal in order to produce leading edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Qp and Qn. 7. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising: a first and a second pulse-width modulator; anda reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein:two vector voltage signals, vp and vn, and two current signals, ip and in, are selected for each operating region;the two voltage signals vp and vn are input to two multipliers and each is multiplied by a voltage signal Vm to form scalable voltage signals (Vp*Vm) and (Vn*Vm);the two scalable voltage signals (Vp*Vm) and (Vn*Vm) are input into two input terminals of a signal adjustment unit to produce two output signals that are respectively sent to two comparators;a clock generates a clock signal, which is used to generate a synchronized sawtooth signal;the ip and in signals are input to a signal adjustment unit having two output signals, and the two output signals are linearly combined with the sawtooth signal and sent to the two comparators; andflip-flops are set by an arrival of the clock signal and reset by a change of state of the comparators, resulting in output signals Qp and Qn. 8. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising: a first and a second pulse-width modulator; anda reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein:two vector voltage signals, vp and vn, and two current signals, ip and in, are selected for each operating region;the two voltage signals vp and vn are input to two multipliers and each is multiplied by a voltage signal Vm to form scalable voltage signals (Vp*Vm) and (Vn*Vm);the two scalable voltage signals (Vp*Vm) and (Vn*Vm) are input into a first signal adjustment unit, the first signal adjustment unit outputting signals to a first set of input terminals of a Schmidt trigger;the ip and in signals are input to a second signal adjustment unit having two cross coupled amplifiers and two adders, the second signal adjustment unit outputting signals to a second set of input terminals of the Schmidt trigger; andthe Schmidt trigger generates variable frequency output signals Qp and Q. 9. A control core, comprising: a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; andan analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is: Vm·[1-dp1-dn]=[2112]·[Rs·ipRs·in]-Ge·ⅇj·θ·[2112]·[vpvn]wherein:Ge is a gain value, θ is a phase offset value,Vm is an output signal of a voltage loop compensator,dp and dn are duty ratio drive signals from the control core,ip and in are selected line current signals from a signal selection unit,Rs is a sensing resistance for the line current signals,vp and vn are selected voltage signals from the signal selection unit, andp and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region. 10. A control core, comprising: a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; andan analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is: Vm·[1-dp1-dn]=[2-1-12]·[Rs·ipRs·in]-Ge·ⅇj·θ·[2-1-12]·[vpvn]wherein:Ge is a gain value, θ is a phase offset value,Vm is an output signal of a voltage loop compensator,dp and dn are duty ratio drive signals from the control core,ip and in are selected line current signals from a signal selection unit,Rs is a sensing resistance for the line current signals,vp and vn are selected voltage signals from the signal selection unit, andp and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region. 11. A control core, comprising: a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; andan analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is Vm·[1-2·dp1-2·dn]=[2-1-12]·[Rs·ipRs·in]-Ge·ⅇj·θ·[2-1-12]·[vpvn]whereinGe is a gain value, θ is a phase offset value,Vm is an output signal of a voltage loop compensator,dp and dn are duty ratio drive signals from the control core,ip and in are selected line current signals from a signal selection unit,Rs is a sensing resistance for the line current signals,vp and vn are selected voltage signals from the signal selection unit, andp and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region. 12. A control core, comprising: a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; andan analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is Vm·[1-dp/21-dn]=12·[2112]·[Rs·ipRs·in]-Ge·ⅇj·θ2·[2112]·[vpvn]whereinGe is a gain value, θ is a phase offset value,Vm is an output signal of a voltage loop compensator,dp and dn are duty ratio drive signals from the control core,ip and in are selected line current signals from a signal selection unit,Rs is a sensing resistance for the line current signals,vp and vn are selected voltage signals from the signal selection unit, andp and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.