Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC
Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC. A column buffer includes a first buffer subsystem, a feedback subsystem, a first and second correlated double sampling subsystem, and a second buffer subsystem. A ROIC includes at least one integration subsystem having a transistor subsection, a poly silicon layer, and a plurality of active layer sections.
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1. A read out integrated circuit (ROIC), comprising a plurality of unit cells, each unit cell including: a bias subsystem connected between a photodiode input and a reset node;a reset switch connected between the reset node and a reset voltage rail;an isolation switch connected between the reset nod
1. A read out integrated circuit (ROIC), comprising a plurality of unit cells, each unit cell including: a bias subsystem connected between a photodiode input and a reset node;a reset switch connected between the reset node and a reset voltage rail;an isolation switch connected between the reset node and an integration node;an integration capacitor connected between the integration node and a top-plate voltage rail; anda read switch connected between the integration node and an output. 2. A method of operating at least one unit cell of the ROIC of claim 1 in a snap-shot mode, comprising the steps of: operating the bias subsystem such that it provides a predetermined bias voltage;executing the following steps one or more times; waiting an integration mode time duration wherein the isolation switch is closed and the reset and read switches are open;opening the isolation switch at an end of the integration mode time duration;waiting a read delay mode time duration;closing the reset switch during the read delay mode time duration;waiting a read mode time duration;closing the read switch for a predetermined amount of time during the read mode time duration;closing the isolation switch at an end of the read mode time duration;waiting a reset mode time duration; andopening the reset switch at an end of the reset mode time duration. 3. The method of claim 2 further comprising operating at least one unit cell in a power down mode or a standby mode while operating at least one unit cell in the snap-shot mode. 4. A method of operating at least one unit cell of the ROIC of claim 1 in a ripple read mode, comprising the steps of: operating the bias subsystem such that it provides a predetermined bias voltage;executing the following steps one or more times: waiting an integration mode time duration wherein the isolation switch is closed and the reset and read switches are open;closing the read switch at an end of the integration mode time duration;waiting a read mode time duration;opening the read switch and closing the reset switch at an end of the read mode time duration;waiting a reset mode time duration; andopening the reset switch at an end of the reset mode time duration. 5. The method of claim 4, further comprising operating at least one unit cell in a power down mode or a standby mode while operating at least one unit cell in the ripple read mode. 6. A method of operating at least one unit cell of the ROIC of claim 1 in a standby mode, comprising the steps of: operating the bias subsystem such that it provides a predetermined bias voltage;closing the reset switch if it is not already closed; andopening the isolation switch if it is not already open. 7. A method of operating at least one unit cell of the ROIC of claim 1, including the steps of: setting a magnitude of the top-plate voltage rail greater than a magnitude of a supply voltage rail for the ROIC; andsetting a high state voltage magnitude of a control signal for the read switch greater than the magnitude of the supply voltage rail for the ROIC. 8. The ROIC of claim 1, wherein the plurality of units cells are grouped into one or more integration subsystems, each integration subsystem including: a first unit cell including: a first bias subsystem connected between a first photodiode input and a first reset node;a first reset switch connected between the first reset node and a first reset voltage rail;a first isolation switch connected between the first reset node and a first integration node;a first integration capacitor connected between the first integration node and a top-plate voltage rail; anda first read switch connected between the first integration node and a first output;a second unit cell including: a second bias subsystem connected between a second photodiode input and a second reset node;a second reset switch connected between the second reset node and a second reset voltage rail;a second isolation switch connected between the second reset node and a second integration node;a second integration capacitor connected between the second integration node and the top-plate voltage rail; anda second read switch connected between the second integration node and a second output; anda connection subsystem operable to connect the first integration node to the second integration node. 9. A method of operating the ROTC of claim 8, comprising the steps of: configuring the connection subsystem of each integration subsystem such that the first integration node is coupled to the second integration node;operating the second unit cell in each integration subsystem in a standby mode, including the following steps:operating the second bias subsystem such that it provides a predetermined bias voltage;closing the second reset switch if it is not already closed; andopening the second isolation switch and the second read switch if they are not already open; andoperating the first unit cell in each integration subsystem in a snap-shot mode, including the following steps:operating the first bias subsystem such that it provides a predetermined bias voltage; andexecuting the following steps one or more times:waiting an integration mode time duration wherein the first isolation switch is closed and the first reset and first read switches are open;opening the first isolation switch at an end of the integration mode time duration;waiting a read delay mode time duration;closing the first reset switch during the read delay mode time duration; waiting a read mode time duration;closing the first read switch for a predetermined amount of time during the read mode time duration;closing the first isolation switch at an end of the read mode time duration; waiting a reset mode time duration; andopening the first reset switch at an end of the reset mode time duration. 10. A method of operating the ROTC of claim 8, comprising the steps of: configuring the connection subsystem of each integration subsystem such that the first integration node is coupled to the second integration node;operating the second unit cell in each integration subsystem in a standby mode, including the following steps: operating the second bias subsystem such that it provides a predetermined bias voltage;closing the second reset switch if it is not already closed; andopening the second isolation switch and the second read switch if they are not already open; andoperating the first unit cell in each integration subsystem in a ripple read mode, including the following steps:operating the first bias subsystem such that it provides a predetermined bias voltage; andexecuting the following steps one or more times: waiting an integration mode time duration, wherein the first reset switch and the first read switch are open and the first isolation switch is closed;closing the first read switch at an end of the integration mode time duration;waiting a read mode time duration;opening the first read switch and closing the first reset switch at an end of the read mode time duration;waiting a reset mode time duration; andopening the first reset switch at an end of the reset mode time duration. 11. The ROTC of claim 1, further comprising an additional read switch connected between the integration node and an additional output. 12. A read out integrated circuit (ROTC), comprising a plurality of unit cells, each unit cell including: a bias subsystem connected between a photodiode input and a first stage node;a reset switch connected between the first stage node and a reset voltage rail;a first capacitor connected between the first stage node and a top-plate voltage rail;a first stage switch connected between the first stage node and a second stage node;a second capacitor connected between the second stage node and the top-plate voltage rail;a second stage switch connected between the second stage node and a third stage node;a third capacitor connected between the third stage node and the top-plate voltage rail; anda read switch connected between the third stage node and an output. 13. A method of operating at least one unit cell of the ROIC of claim 12 in a snap-shot, averaging mode, comprising the steps of: operating the bias subsystem such that it provides a predetermined bias voltage;executing the following steps one or more times: waiting an initial integration mode time duration, wherein the read switch and the second stage switch are open, the first stage switch is closed, and the reset switch is initially closed;opening the reset switch during the initial integration mode time duration;opening the first stage switch at an end of the initial integration mode time duration;waiting an initial reset mode time duration;closing the reset switch and the second stage switch at about a same time during the initial reset mode time duration;executing the following steps one or more times: opening the second stage switch;waiting an integration mode time duration;closing the first stage switch during the integration mode time duration;opening the reset switch subsequent to closing the first stage switch during the integration mode time duration;opening the first stage switch at an end of the integration mode time duration;waiting a reset mode time duration; andclosing the reset switch and the second stage switch at about a same time during the reset mode time duration;waiting a read delay mode time duration;closing the read switch at an end of the read delay mode time duration;waiting a read mode time duration;opening the read switch and closing the first stage switch at an end of the read mode time duration;waiting a post read mode time duration; andopening the second stage switch at an end of the post read mode time duration. 14. The method of claim 13, further comprising operating at least one unit cell in a power down mode while operating at least one unit cell in the snap-shot; averaging mode. 15. A method of operating at least one unit cell of the ROIC of claim 12 in a snap-shot, direct integration mode, comprising the steps of: operating the bias subsystem such that it provides a predetermined bias voltage;closing the second stage switch if it is not already closed;executing the following steps one or more times:waiting an integration mode time duration wherein the first stage switch is closed and the reset switch and the read switch are open;opening the first stage switch at an end of the integration mode time duration;waiting a read delay mode time duration;closing the reset switch during the read delay mode time duration;waiting a read mode time duration;closing the read switch for a predetermined amount of time during the read mode time duration;closing the first stage switch at an end of the read mode time duration;waiting a reset mode time duration; andopening the reset switch at an end of the reset mode time duration. 16. The method of claim 15, further comprising operating at least one unit cell in a power down mode while operating at least one unit cell in the snap-shot, direct integration mode. 17. A method of operating at least one unit cell of the ROIC of claim 12, including the steps of: operating the unit cell in a snap-shot, averaging mode if a flux density of light received by a photodiode connected to the photodiode input is above a predetermined threshold; andoperating the unit cell in a snap-shot, direct integration mode if the flux density of light received by the photodiode connected to the photodiode input is below the predetermined threshold. 18. A method of operating at least one unit cell of the ROIC of claim 12 in a standby mode, comprising the steps of operating the bias subsystem such that it provides a predetermined bias voltage;closing the reset switch if it is not already closed; andopening the first stage switch if it is not already open. 19. The ROIC of claim 12, wherein the plurality of units cells are grouped into one or more integration subsystems, each integration subsystem including: a first unit cell; anda second unit cell. 20. A method of operating at least one unit cell of the ROIC of claim 12, including the step of: setting a voltage magnitude of the top-plate voltage rail greater than a voltage magnitude of a supply voltage rail for the ROIC; andsetting high state voltage magnitudes of control signals for the first stage switch, the second stage switch, and the read switch greater than the voltage magnitude of the supply voltage rail for the ROIC. 21. The ROIC of claim 12, further comprising a second read switch connected between the third stage node and a second output. 22. A focal plane array (FPA), comprising: a plurality of photo detectors disposed in a grid, the grid having a plurality of horizontal rows of photo detectors and a plurality of vertical columns of photo detectors, each photo detector having a first color photodiode and a second color photodiode; anda read out integrated circuit (ROIC) including: an integration subsystem coupled to each photo detector, each integration subsystem including:a first unit cell having a photodiode input coupled to the first color photodiode of a respective photo detector; anda second unit cell having a photodiode input coupled to the second color photodiode of the respective photo detector;a first column buffer and a second column buffer for each column of photo detectors;a first bus for each column of photo detectors, the first bus connecting an output of each first unit cell of the column to an input of the first column buffer of the column;a second bus for each column of photo detectors, the second bus connecting an output of each second unit cell of the column to an input of the second column buffer of the column;a control switching subsystem connected to an output of each column buffer; andat least one output driver connected to the control switching subsystem. 23. The FPA of claim 22, wherein each first unit cell and each second unit cell further comprise: a bias subsystem connected between the photodiode input and a reset node;a reset switch connected between the reset node and a reset voltage rail;an isolation switch connected between the reset node and an integration node;an integration capacitor connected between the integration node and a top-plate voltage rail; anda read switch connected between the integration node and an output. 24. A method of operating the FPA of claim 23, comprising the step of independently controlling a frame rate of one or more first unit cells independently of a frame rate of one or more second unit cells. 25. A method of operating the FPA of claim 23, comprising the steps of: configuring each horizontal row of pixels such that a first quantity of first pixels are active and a first quantity of second pixels are active; andconfiguring each vertical column of pixels such that a second quantity of first pixels are active and a second quantity of second pixels are active. 26. A method of operating the FPA of claim 23, comprising the step of operating each first unit cell in a snap-shot mode and operating each second unit cell in a ripple read mode. 27. A method of operating the FPA of claim 23, comprising the step of configuring the FPA such that solely every second pixel of every second row of pixels is active. 28. A method of operating the FPA of claim 23, comprising the step of configuring the FPA such that solely every fourth pixel of every fourth row of pixels is active. 29. The FPA of claim 22, further comprising a connection subsystem in each integration subsystem, the connection subsystem operable to connect an integration node of the first unit cell to an integration node of the second unit cell. 30. A method of operating the FPA of claim 22, comprising the steps of: reading an odd row of first unit cells via the first or second bus while reading an adjacent even row of first unit cells via a bus not used for reading the odd row of first unit cells; andreading an odd row of second unit cells via the first or second bus while reading an adjacent even row of second unit cells via a bus not used for reading the odd row of second unit cells, the second unit cells being read at a different time than the first unit cells. 31. A method of operating the FPA of claim 22, comprising the steps of: reading a first set of pixels having a first integration mode time duration at an end of the first integration mode time duration; andreading a second set of pixels having a second integration mode time duration at an end of the second integration mode time duration, the second integration mode time duration being greater than the first integration mode time duration. 32. The FPA of claim 22, wherein each first unit cell and each second unit cell further comprise: a bias subsystem connected between the photodiode input and a first stage node;a reset switch connected between the first stage node and a reset voltage rail;a first capacitor connected between the first stage node and a top-plate rail;a first stage switch connected between the first stage node and a second stage node;a second capacitor connected between the second stage node and the top-plate rail;a second stage switch connected between the second stage node and a third stage node;a third capacitor connected between the third stage node and the top-plate rail; anda read switch connected between the third stage node and an output. 33. The FPA of claim 22, wherein: the first unit cell further comprises: a bias subsystem connected between the photodiode input and a first stage node;a reset switch connected between the first stage node and a reset voltage rail;a first capacitor connected between the first stage node and a top-plate voltage rail;a first stage switch connected between the first stage node and a second stage node;a second capacitor connected between the second stage node and the top-plate voltage rail;a second stage switch connected between the second stage node and a third stage node;a third capacitor connected between the third stage node and the top-plate voltage rail; anda read switch connected between the third stage node and an output; andthe second unit cell further comprises:a bias subsystem connected between the photodiode input and a reset node;a reset switch connected between the reset node and a reset voltage rail;an isolation switch connected between the reset node and an integration node an integration capacitor connected between the integration node and a top-plate voltage rail; anda read switch connected between the integration node and an output. 34. The FPA of claim 33, wherein: each first color photodiode is optimized to capture long wave infrared light; andeach second color photodiode is optimized to capture medium wave infrared light. 35. A method of operating the FPA of claim 33, comprising the steps of: operating each first unit cell in a snap-shot, averaging mode if a flux density of light received by the first color photodiodes is above a predetermined threshold; andoperating each first unit cell in a snap-shot, direct integration mode if the flux density of light received by the first color photodiodes is below the predetermined threshold. 36. A method of operating the FPA of claim 22, comprising the step of controlling operation of each first unit cell independently of operation of each second unit cell. 37. The FPA of claim 22 further comprising: at least one horizontal scanner;at least one vertical scanner;at least one bias generator; andat least one control subsystem. 38. A column buffer, comprising: a first buffer subsystem having an input connected to an input node and an output connected to a first buffered node;a feedback subsystem connected between the input node and the first buffered node;a first correlated double sampling (CDS) subsystem connected between the first buffered node and a CDS output node;a second CDS subsystem connected between the first buffered node the CDS output node; anda second buffer subsystem including: an input connected to the CDS output node;an output connected to a column buffer bus node; andan enable input operable to control an operating state of the second buffer subsystem. 39. A method of operating the column buffer of claim 38, comprising configuring the feedback subsystem such that it has a capacitance value about equal to an integration capacitance of a unit cell connected to the input node. 40. A method of operating the column buffer of claim 38, comprising operating the first and second CDS subsystems in manner such one of the CDS subsystems is a reading a signal from the first buffered node while the other CDS subsystem is transferring a previously read signal to the CDS output node. 41. The column buffer of claim 38, wherein: the feedback subsystem includes: a first feedback switch connected between the input node and the first buffered node;a variable capacitor connected between the input node and an internal feedback node;a third feedback third switch connected between the internal feedback node and the first buffered node; anda second feedback switch connected between the internal feedback node and a feedback clamping voltage rail;the first CDS subsystem and the second CDS subsystem each include: a first CDS switch connected between the first buffered node and a first CDS node;a first CDS capacitor connected between the first CDS node and a common node;a second CDS capacitor connected between the first CDS node and a second CDS node;a second CDS switch connected between the second CDS node and the CDS output node; anda third CDS switch connected between the second CDS node and a CDS clamping voltage rail; anda reset switch connected between the CDS output node and a column reset voltage rail. 42. The column buffer of claim 41, wherein the variable capacitor further comprises at least one capacitance cell; each capacitance cell including: a unit capacitor connected between the internal feedback node and a cell center node;a control switch connected between the cell center node and the input node; anda clamping switch connected between the cell center node and the common node. 43. A method of operating the column buffer of claim 42, comprising the step of operating the control switch and the clamping switch in a complementary fashion. 44. A read out integrated circuit (ROIC), comprising at least one integration subsystem, each integration subsystem including: a transistor subsection including: a nwell including: a p-channel depletion metal oxide field effect transistor of a biasing subsystem of a first unit cell; anda p-channel depletion metal oxide field effect transistor of a biasing subsystem of a second unit cell; andan n-channel depletion metal oxide field effect transistor subsection;a horizontal poly silicon layer adjacent to three sides of the transistor subsection; anda plurality of horizontal active layer sections disposed below the poly silicon layer, wherein each active layer section extends horizontally beyond an outline of the poly silicon layer solely along sides of the active layer section adjacent to the transistor subsection. 45. The ROTC of claim 44, wherein the nwell further comprises a p-channel depletion metal oxide field effect transistor of a connection subsystem. 46. The ROTC of claim 44 further comprising two active layer sections. 47. The ROTC of claim 44 further comprising six active layer sections. 48. The ROTC of claim 44 further comprising a plurality of integration subsystems disposed in a common horizontal plane, the poly silicon layers of each integration subsystem mechanically and electrically coupled together.
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이 특허에 인용된 특허 (10)
Martin Robert J. (Orlando FL) Reiff Kirk (Titusville FL) West Mark (Oviedo FL) Milne Gregory L. (Casselberry FL) Brown Kevin (Orlando FL), Apparatus for and method of providing long integration times in an IR detector.
Finch, James A.; Graham, Roger W.; Black, Stephen H.; Wilson, Jerry A.; Wyles, Richard H., IRFPA ROIC with dual TDM reset integrators and sub-frame averaging functions per unit cell.
Caulfield John T. ; Wyles Richard H. ; Schlesselmann John D. ; Pettijohn Kevin L., Multipurpose readout integrated circuit with in cell adaptive non-uniformity correction and enhanced dynamic range.
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