Virtual machine management using processor state information
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/455
G06F-009/46
G06F-015/173
출원번호
US-0176925
(2008-07-21)
등록번호
US-8296762
(2012-10-23)
발명자
/ 주소
Knauerhase, Robert C.
Tewari, Vijay
출원인 / 주소
Intel Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
6인용 특허 :
138
초록
A method, system, and apparatus are provided for virtual machine management. According to one embodiment, processor state information associated with a processor is evaluated, and the processor state information is used to manage one or more virtual machines.
대표청구항▼
1. A method comprising: monitoring processor state information relating to a processor;gathering the processor state information, wherein the processor state information provides processor state relating to one or more of characteristics of the processor, history of the processor, characteristics of
1. A method comprising: monitoring processor state information relating to a processor;gathering the processor state information, wherein the processor state information provides processor state relating to one or more of characteristics of the processor, history of the processor, characteristics of a plurality of virtual machines associated with the processor, history of the plurality of virtual machines, and event monitoring data; andmanaging, using the processor state information, the plurality of virtual machines including a first virtual machine and a second virtual machine, wherein managing includes managing the characteristics of the processor and predetermined time slices allocated to each of the first virtual machine and the second virtual machine, and dynamically allocating resources to the first virtual machine or the second virtual machine, wherein dynamically allocating includes alternating between the first virtual machine and the second virtual machine, wherein alternating includes switching tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine based on the information and reallocating the predetermined time slices from the first virtual machine to the second virtual machine, wherein the second virtual machine is determined to be better based on the characteristics of the processor and independent of the predetermined allocated time slices. 2. The method of claim 1, wherein the managing of the first and second virtual machines is performed by a virtual machine manager (VMM) comprising a state management unit. 3. A system comprising: a storage medium to store information relating to a processor coupled with the storage medium; anda processor having a virtual machine manager (VMM), wherein the VMM tomonitor processor state information relating to a processor,gather the processor state information, wherein the processor state information provides processor state relating to one or more of characteristics of the processor, history of the processor, characteristics of a plurality of virtual machines associated with the processor, history of the plurality of virtual machines, and event monitoring data, andmanage, using the processor state information, the plurality of virtual machines including a first virtual machine and a second virtual machine, wherein managing includes managing the characteristics of the processor and predetermined time slices allocated to each of the first virtual machine and the second virtual machine, and dynamically allocating resources to the first virtual machine or the second virtual machine, wherein dynamically allocating includes alternating between the first virtual machine and the second virtual machine, wherein alternating includes switching tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine based on the information and reallocating the predetermined time slices from the first virtual machine to the second virtual machine, wherein the second virtual machine is determined to be better based on the characteristics of the processor and independent of the predetermined allocated time slices. 4. The system of claim 3, wherein the processor comprises one or more of microprocessors, hyperthreaded processors, digital signal processors, and microcontrollers. 5. The system of claim 3, wherein the first and second virtual machines comprise guest software, the guest software having one or more of an operating software and a software application. 6. A non-transitory machine-readable medium comprising instructions stored thereon which, when executed by a machine, cause the machine to: monitor processor state information relating to a processor;gather the processor state information, wherein the information provides processor state relating to one or more of characteristics of the processor, history of the processor, characteristics of a plurality of virtual machines associated with the processor, history of the plurality of virtual machines, and event monitoring data; andmanage, using the processor state information, the plurality of virtual machines including a first virtual machine and a second virtual machine, wherein managing includes managing the characteristics of the processor and predetermined time slices allocated to each of the first virtual machine and the second virtual machine, and dynamically allocating resources to the first virtual machine or the second virtual machine, wherein dynamically allocating includes alternating between the first virtual machine and the second virtual machine, wherein alternating includes switching tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine based on the information and reallocating the predetermined time slices from the first virtual machine to the second virtual machine, wherein the second virtual machine is determined to be better based on the characteristics of the processor and independent of the predetermined allocated time slices. 7. The non-transitory machine-readable medium of claim 6, wherein the managing of the first and second virtual machines is performed by a virtual machine manager (VMM) comprising a state management unit. 8. A method comprising: allocating a first predetermined time slice to a first virtual machine, and a second predetermined time slice to a second virtual machine at a computing system;switching tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine, wherein the second virtual machine is determined to be better based on characteristics of a processor and independent of the predetermined allocated time slices, wherein the processor is associated with the first and second virtual machines, wherein the characteristics of the processor is obtained from processor state information relating to the processor of the computing system;suspending the first predetermined processing time allocated to the first virtual machine; andextending the second predetermined processing time allocated to the second virtual machine by granting the suspended first predetermined processing time of the first virtual machine to the second virtual machine. 9. The method of claim 8, wherein the processor state information further provides historical information relating to the processor. 10. The method of claim 8, wherein the processor state information further provides one or more of characteristic information relating to the first virtual machine or the second virtual machine, historical information relating to the first virtual machine or the second virtual machines, and event monitoring data. 11. A system comprising: a storage medium having stored thereon instructions; anda processor coupled to the storage medium, wherein the instructions when executed by the processor, cause the processor to:allocate a first predetermined time slice to a first virtual machine, and a second predetermined time slice to a second virtual machine at a computing system;switch tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine, wherein the second virtual machine is determined to be better based on characteristics of a processor and independent of the predetermined allocated time slices, wherein the processor is associated with the first and second virtual machines, wherein the characteristics of the processor is obtained from processor state information relating to the processor of the computing system;suspend the first predetermined processing time allocated to the first virtual machine; andextend the second predetermined processing time allocated to the second virtual machine by granting the suspended first predetermined processing time of the first virtual machine to the second virtual machine. 12. The system of claim 11, wherein the processor state information further provides historical information relating to the processor. 13. The system of claim 11, wherein the processor state information further provides one or more of characteristic information relating to the first virtual machine or the second virtual machine, historical information relating to the first virtual machine or the second virtual machines, and event monitoring data. 14. A non-transitory machine-readable medium having stored thereon instructions which, when executed by a machine, cause the machine to: allocate a first predetermined time slice to a first virtual machine, and a second predetermined time slice to a second virtual machine at a computing system;switch tasks being performed on the first virtual machine to the second virtual machine when the second virtual machine is determined to be better at performing the tasks than the first virtual machine, wherein the second virtual machine is determined to be better based on characteristics of a processor and independent of the predetermined allocated time slices, wherein the processor is associated with the first and second virtual machines, wherein the characteristics of the processor is obtained from processor state information relating to the processor of the computing system;suspend the first predetermined processing time allocated to the first virtual machine; andextend the second predetermined processing time allocated to the second virtual machine by granting the suspended first predetermined processing time of the first virtual machine to the second virtual machine. 15. The non-transitory machine-readable medium of claim 14, wherein the processor state information provides historical information relating to the processor. 16. The non-transitory machine-readable medium of claim 14, wherein the processor state information further provides one or more of characteristic information relating to the first virtual machine or the second virtual machine, historical information relating to the first virtual machine or the second virtual machines, and event monitoring data.
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이 특허에 인용된 특허 (138)
Hatada Minoru (Ebina JPX) Ishida Hideaki (Kawasaki JPX) Matsushita Masatoshi (Kawasaki JPX), Access control method for multiprocessor systems.
Gannon Patrick M. (Poughkeepsie NY) Gum Peter H. (Poughkeepsie NY) Hough Roger E. (Highland NY) Murray Robert E. (Woodstock NY), Apparatus and method for TLB purge reduction in a multi-level machine system.
Bealkowski Richard (Delray Beach FL) Blackledge ; Jr. John W. (Boca Raton FL) Cronk Doyle S. (Boca Raton FL) Dayan Richard A. (Boca Raton FL) Dixon Jerry D. (Boca Raton FL) Kinnear Scott G. (Boca Rat, Apparatus and method for preventing unauthorized access to BIOS in a personal computer system.
Heller Andrew R. (Morgan Hill CA) Worley ; Jr. William S. (Endicott NY), Authorization mechanism for transfer of program control or data between different address spaces having different storag.
Ermolovich Thomas R. (Lexington MA) Stewart Robert E. (Stow MA) Leonard Judson S. (Acton MA) Cutler David N. (Nashua NH), Communications device for data processing system.
Satou Mitsugu,JPX ; Iwata Shunichi,JPX, Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple memory zones in an isolated execution environment.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Executing isolated mode instructions in a secure system running in privilege rings.
Nakamura Kouji,JPX, Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice.
Schneider Fred B. (Ithaca NY) Lampson Butler (Cambridge MA) Balkovich Edward (Acton MA) Thiel David (Colorado Springs CO), Fault tolerant computer system with shadow virtual processor.
Adams Phillip M. (Parowan UT) Holmstron Larry W. (Salt Lake City UT) Jacob Steve A. (South Weber UT) Powell Steven H. (Ogden UT) Condie Robert F. (Tuscon AZ) Culley Martin L. (Tuscon AZ), Kernels, description tables, and device drivers.
Lim, Beng-Hong; Bugnion, Edouard; Devine, Scott W., Mechanism for restoring, porting, replicating and checkpointing computer systems using state extraction.
Barnett Philip C.,GBX, Memory management method and apparatus for partitioning homogeneous memory and restricting access of installed applications to predetermined memory ranges.
Chemin Francois (Plaisir FRX) Ugon Michel (Maurepas FRX), Method and apparatus for certifying services obtained using a portable carrier such as a memory card.
Harold L. McFarland ; David R. Stiles ; Korbin S. Van Dyke ; Shrenik Mehta ; John Gregory Favor ; Dale R. Greenley ; Robert A. Cargnoni, Method and apparatus for debugging an integrated circuit.
Miller David A. ; Jansen Kenneth A. ; Culley Paul R. ; Taylor Mark ; Izquierdo Javier F., Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
Cotichini Christian,CAX ; Cain Fraser,CAX ; Ashworth David G.,CAX ; Livingston Peter Michael Bruce,CAX ; Solymar Gabor,CAX ; Gardner Philip B.,CAX ; Woinoski Timothy S.,CAX, Method and apparatus to monitor and locate an electronic device using a secured intelligent agent.
Kahle James Allan ; Loper Albert J. ; Mallick Soummya ; Ogden Aubrey Deene ; Sell John Victor, Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions w.
Hazard Michel (Mareil/Mauldre FRX) Ugon Michel (Maurepas FRX), Method for authenticating an external authorizing datum by a portable object, such as a memory card.
Melo Michael D. (Billerica MA), Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 8048.
Hazard Michel (Mareil/Mauldre FRX), Method for certifying the authenticity of a datum exchanged between two devices connected locally or remotely by a trans.
Ugon Michel (Maurepas FRX) Oisel Andr (Elancourt FRX), Method for checking the integrity of a program or data, and apparatus for implementing this method.
Ganapathy Narayanan ; Stevens Luis F. ; Schimmel Curt F., Method, system and computer program product for dynamically allocating large memory pages of different sizes.
Eugene Feng ; Gary Phillips, Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space.
Grimmer ; Jr. George G. ; Rhoades Michael W., Microcontroller with security logic circuit which prevents reading of internal memory by external program.
Goetz John W. ; Mahin Stephen W. ; Bergkvist John J., Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set archi.
Blomgren James S. (San Jose CA) Bracking Jimmy (San Jose CA) Richter David (San Jose CA) Spahn Francis (El Cerrito CA), Microprocessor with operation capture facility.
Reardon David C., Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place.
Provanzano Salvatore R. (Melrose MA) Aldrich Wilbert H. (Winchester MA) D\Angelo Robert A. (Windham NH) Drottar Emil P. (Ipswich MA) Finnegan ; Jr. John J. (Hudson NH) Heom James (Bedford MA) Hill La, Programmable controller.
Robinson Paul T. (Arlington MA) Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA), Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Goire Christian (Les Clayes Sous Bois FRX) Sigaud Alain (Elancourt FRX) Moyal Eric (Paris FRX), Safeguarded remote loading of service programs by authorizing loading in protected memory zones in a terminal.
Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
Hudson Jerome D. ; Champagne Jean-Paul,FRX ; Galindo Mary A. ; Hickerson Cynthia M. K. ; Hickman Donna R. ; Lockhart Robert P. ; Saddler Nancy B. ; Stange Patricia A., System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential.
Angelo Michael F. ; Olarig Sompong P. ; Wooten David R. ; Driscoll Dan J., System and method for performing secure device communications in a peer-to-peer bus architecture.
Inoue Taro (Sagamihara JPX) Umeno Hidenori (Kanagawa JPX) Tanaka Shunji (Sagamihara JPX) Yamamoto Tadashi (Kanagawa JPX) Ohtsuki Toru (Hadano JPX), System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard T. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant player for scrambled contents.
Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA) Robinson Paul T. (Arlington MA) Witek Richard T. (Littleton MA), Translation buffer for virtual machines with address space match.
Matsuura Hidekazu (Kawasaki JPX), Virtual computer control system effectively using a CPU with predetermined assignment ratios of resources based on a fir.
Scott W. Devine ; Edouard Bugnion ; Mendel Rosenblum, Virtualization system including a virtual machine monitor for a computer with a segmented architecture.
DeHaan, Michael Paul; Hinson, Bradford E.; Laska, James; Payne, Robert Justin; Perkins, Brandon, Management of mainframe resources in pre-boot environment.
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