초록 ▼

The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges a

The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph; searching for all directed cycles of the directed graph; and for each directed cycle, if the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle. The method and apparatus can automatically detect timing constraint conflicts with one hundred percent to reduce design turnaround time and engineer resources in ASIC projects.

대표청구항 ▼

1. A method for detecting timing constraint conflicts, comprising: receiving a timing constraint file;taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test poi

1. A method for detecting timing constraint conflicts, comprising: receiving a timing constraint file;taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph which comprises: parsing general timing constraints, and taking all obtained test points as nodes, wherein the general timing constraints comprise at least one of implicit timing constraints and timing constraints given in the timing constraint file;obtaining directed edges between all the nodes and weights of the directed edges according to parsed general timing constraints; andforming a directed graph by using all the nodes, the directed edges and the weights on the directed edges;searching for all directed cycles of the directed graph; andfor each directed cycle, after determining that the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle;wherein the method is performed by one or more computer processors. 2. The method as recited in claim 1, wherein the weight of a directed edge is Minimum Required Time Advanced of signal arrival of two nodes connected by that directed edge. 3. The method as recited in claim 1 or 2, wherein taking the test points in the timing constraint file as nodes further comprises: determining whether information of all the test points in the timing constraint file are complete; andafter determining that information of part of the test points are incomplete, conducting a retrieval in a netlist to obtain complete information of the part of the test points. 4. The method as recited in claim 1, wherein parsing general timing constraints comprises: retrieving implicit timing constraints in the netlist, the implicit timing constraints are defined by devices used in the netlist and are not given in the timing constraint file; andcombining the implicit timing constraints with the timing constraints given in the timing constraint file to form general timing constraints. 5. The method as recited in claim 1 or 2, wherein after determining that the directed edges point to nodes at which signal arrives at a late time, the condition required to be satisfied by the sum of the weights of the directed edges constituting the directed cycle is that the sum of the weights is larger than 0. 6. The method as recited in claim 1 or 2, wherein after determining that the directed edges point to nodes at which signal arrives at an early time, the condition required to be satisfied by the sum of the weights of the directed edges constituting the directed cycle is that the sum of the weights is smaller than 0. 7. The method as recited in claim 1 or 2, wherein searching for all directed cycles of the directed graph comprises searching for all strongly connected components of the directed graph. 8. The method as recited in claim 1 or 2, further comprising: outputting the test points and timing constraints constituting the directed cycle among which the timing constraint conflict exists. 9. An apparatus for detecting timing constraint conflicts, comprising: a receiving module for receiving a timing constraint file;an establishing module for, taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph, the establishing module comprises: a parsing module for parsing general timing constraints, and taking all obtained test points as nodes, wherein the general timing constraints comprise at least one of implicit timing constraints and timing constraints given in the timing constraint file;a directed edge and weight establishing module for obtaining directed edges between all the nodes and weights of the directed edges according to parsed general timing constraints; anda directed graph establishing module for forming a directed graph by using all the nodes, the directed edges and the weights on the directed edges;a searching module for searching for all directed cycles of the directed graph; anda determining module for, for each directed cycle, after determining that the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle. 10. The apparatus as recited in claim 9, wherein the weight of a directed edge is Minimum Required Time Advanced of signal arrival of two nodes connected by that directed edge. 11. The apparatus as recited in claim 9 or 10, wherein the establishing module comprises: a judging module for judging whether information of all the test points in the timing constraint file are complete; anda netlist retrieval module for, if information of part of the test points are incomplete, conducting a retrieval in the netlist to obtain complete information of the part of the test points. 12. The apparatus as recited in claim 10, wherein the parsing module comprises: a netlist retrieval module for retrieving implicit timing constraints in the netlist, the implicit timing constraints are defined by devices used in the netlist and are not given in the timing constraint file; anda combining module for combining the implicit timing constraints with the timing constraints given in the timing constraint file to form general timing constraints. 13. The apparatus as recited in claim 9 or 10, wherein if after determining that the directed edges point to nodes at which signal arrives at a late time, the condition required to be satisfied by the sum of the weights of the directed edges constituting the directed cycle is that the sum of the weights is larger than 0. 14. The apparatus as recited in claim 9 or 10, wherein if after determining that the directed edges point to nodes at which signal arrives at an early time, the condition required to be satisfied by the sum of the weights of the directed edges constituting the directed cycle is that the sum of the weights is smaller than 0. 15. The apparatus as recited in claim 9 or 10, wherein the searching module comprises: a strongly connected component searching module for searching for all strongly connected components of the directed graph. 16. The apparatus as recited in claim 9 or 10, further comprising: an outputting module for outputting the test points and timing constraints constituting the directed cycle among which the timing constraint conflict exists.