IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0590133
(2006-10-31)
|
등록번호 |
US-8304342
(2012-11-06)
|
발명자
/ 주소 |
- Pas, Michael Francis
- Ramin, Manfred
|
출원인 / 주소 |
- Texas Instruments Incorporated
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
14 |
초록
A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.
대표청구항
▼
1. A method of forming a semiconductor device, comprising: forming a gate stack over a semiconductor substrate, the gate stack having a height and including a layer of gate dielectric material formed over the substrate, a layer of gate electrode material including polysilicon formed over the layer o
1. A method of forming a semiconductor device, comprising: forming a gate stack over a semiconductor substrate, the gate stack having a height and including a layer of gate dielectric material formed over the substrate, a layer of gate electrode material including polysilicon formed over the layer of gate dielectric material, and a layer of silicon-germanium (SiGe) material formed over and in direct contact with the layer of gate electrode material;forming a layer of first dielectric material over the gate stack and over regions of the substrate adjacent to the gate stack;forming a layer of second dielectric material over the layer of first dielectric material, the layers of first and second dielectric materials having a combined thickness greater than the height of the gate stack;performing a chemical mechanical polishing (CMP) process to planarize the layers of first and second dielectric materials down to expose the layer of silicon-germanium material;following the chemical mechanical polishing (CMP) process, selectively chemically etching the layer of silicon-germanium material using an etchant to expose the polysilicon;following the chemically etching, forming a blanket layer of siliciding material over the planarized layers of first and second dielectric materials and over the exposed polysilicon; andreacting the siliciding material with the polysilicon to form a silicide. 2. The method of claim 1, wherein one of the first and second dielectric materials comprising a nitride; the other of the first and second dielectric materials comprises an oxide; and the etchant is a wet etchant selective to the polysilicon and to the nitride and the oxide. 3. The method of claim 2, wherein the etchant comprises an ammonia hydrogen peroxide solution (NH4OH:H2O2:H2O). 4. The method of claim 2, wherein the nitride comprises silicon nitride and the oxide comprises tetraethyl orthosilicate (TEOS). 5. The method of claim 1, wherein the gate stack further includes a nitride hardmask formed over the layer of silicon-germanium material, and the nitride hardmask is removed prior to forming the layer of first dielectric material. 6. The method of claim 5, further comprising forming sidewall spacers on sides of the gate stack, and implanting dopant to form source/drain regions in the substrate adjacent the sidewall spacers; and wherein the layer of first dielectric material is formed over the source/drain regions. 7. The method of claim 6, further comprising forming source/drain extension regions in the substrate. 8. The method of claim 6, wherein the etchant is selective to the polysilicon and to material of the sidewall spacers. 9. The method of claim 1, wherein the layer of gate dielectric material is formed to a thickness of between about 10 and about 50 Angstroms; the layer of gate electrode material is formed to a thickness of between about 500 and about 1500 Angstroms; and the layer of silicon-germanium is formed to a thickness of between about 100 and about 500 Angstroms. 10. The method of claim 9, wherein the layer of first dielectric material is formed to a thickness of between about 150 and about 350 Angstroms; and the layer of second dielectric material is formed to a thickness of between about 400 and about 2000 Angstroms. 11. The method of claim 10, wherein the gate stack further includes a layer of hardmask material formed over the layer of silicon-germanium material to a thickness of between about 200 and about 500 Angstroms. 12. The method of claim 11, wherein the first dielectric material comprises a nitride, the second dielectric material comprises an oxide, the hardmask material comprises a nitride, and the etchant comprises an ammonia hydrogen peroxide solution (NH4OH:H2O2:H2O). 13. The method of claim 1, wherein reacting the siliciding material comprises performing a first thermal process to partially silicide the polysilicon; removing unreacted portions of the siliciding material after performing the first thermal process; and performing a second thermal process to fully silicide the polysilicon after removing the unreacted portions. 14. The method of claim 1, wherein the siliciding material comprises nickel (Ni); and reacting the siliciding material comprises performing a first thermal process at a temperature of between about 300° C. and about 450° C. to form a first state nickel silicide, removing unreacted portions of the nickel following the first thermal process, and performing a second thermal process at a temperature of between about 400° C. and about 550° C. to form a second state nickel silicide after removing the unreacted portions. 15. The method of claim 1, wherein the layer of gate electrode material is formed to be at least three times thicker than the layer of silicon-germanium. 16. A method of forming a semiconductor device, comprising: forming a gate stack over a semiconductor substrate, the gate stack having a height and including a layer of gate dielectric material formed over the substrate, a layer of gate electrode material including polysilicon formed over the layer of gate dielectric material, a layer of silicon-germanium (SiGe) material formed over and in direct contact with the layer of gate electrode material, and a layer of hardmask material formed over the layer of silicon-germanium material;forming sidewall spacers on sides of the gate stack;implanting dopant to form source/drain regions in the substrate adjacent the sidewall spacers;forming a layer of nitride dielectric material over the gate stack and over the source/drain regions;forming a layer of oxide dielectric material over the layer of nitride dielectric material, the layers of nitride and oxide dielectric materials having a combined thickness greater than the height of the gate stack;performing a chemical mechanical polishing (CMP) process to planarize the layers of nitride and oxide dielectric materials down to expose the layer of silicon-germanium material;following the chemical mechanical polishing (CMP) process, selectively chemically wet etching the layer of silicon-germanium material using an etchant selective to polysilicon, to the nitride dielectric material and to the oxide dielectric material to expose the polysilicon;following the wet etching, forming a blanket layer of siliciding metal over the planarized layers of nitride and oxide dielectric materials and over the exposed polysilicon; andreacting the siliciding metal with the polysilicon to form a metal silicide. 17. The method of claim 16, wherein the nitride comprises silicon nitride, the oxide comprises tetraethyl orthosilicate (TEOS), and the etchant comprises an ammonia hydrogen peroxide solution (NH4OH:H2O2:H2O). 18. The method of claim 17, wherein the sidewalls comprise a first layer of an oxide material and a second layer of a nitride material. 19. The method of claim 16, wherein the layer of hardmask material comprises a nitride hardmask material; and the nitride hardmask material is removed prior to forming the layer of nitride dielectric material. 20. The method of claim 16, wherein the layer of gate electrode material is formed to be three to five times thicker than the layer of silicon-germanium. 21. The method of claim 16, wherein reacting the siliciding metal comprises performing a first thermal process to partially silicide the polysilicon; removing unreacted portions of the siliciding metal after the first thermal process; and performing a second thermal process to fully silicide the polysilicon after removing the unreacted portions. 22. The method of claim 21, wherein the siliciding metal comprises nickel (Ni). 23. A method of forming a semiconductor device, comprising: forming a gate stack over a semiconductor substrate, including a layer of gate dielectric material including at least one of silicon oxide or a high-k dielectric material formed over the substrate, a layer of gate electrode material including polysilicon formed over the layer of gate dielectric material, a layer of silicon-germanium (SiGe) material formed over and in direct contact with the layer of gate electrode material, and a layer of nitride hardmask material formed over the layer of silicon-germanium material; the gate stack having a height and the layer of gate electrode material being at least three times thicker than the layer of silicon-germanium;forming sidewall spacers on sides of the gate stack;implanting dopant to form source/drain regions in the substrate adjacent the sidewall spacers;removing the layer of nitride hardmask material;forming a layer of nitride dielectric material comprising silicon nitride over the gate stack and over the source/drain regions;forming a layer of oxide dielectric material comprising tetraethyl orthosilicate (TEOS) over the layer of nitride dielectric material, the layers of nitride and oxide dielectric materials having a combined thickness greater than the height of the gate stack;performing a single chemical mechanical polishing (CMP) process to planarize the layers of nitride and oxide dielectric materials down to expose the layer of silicon-germanium material;following the chemical mechanical polishing (CMP) process, selectively chemically wet etching the layer of silicon-germanium material using an etchant comprising an ammonia hydrogen peroxide solution (NH4OH:H2O2:H2O) to expose the polysilicon;following the chemically wet etching, forming a blanket layer of siliciding metal over the planarized layers of nitride and oxide dielectric materials and over the exposed polysilicon; andthermally reacting the siliciding metal with the polysilicon to form a metal silicide. 24. The method of claim 23 wherein the sidewalls comprise layers of oxide and nitride materials. 25. The method of claim 24, wherein the layer of gate dielectric material is formed to a thickness of between about 10 and about 50 Angstroms; the layer of gate electrode material is formed to a thickness of between about 500 and about 1500 Angstroms; the layer of silicon-germanium is formed to a thickness of between about 100 and about 500 Angstroms; the layer of hardmask material is formed to a thickness of between about 200 and about 500 Angstroms; the layer of nitride dielectric material is formed to a thickness of between about 150 and about 350 Angstroms; and the layer of oxide dielectric material is formed to a thickness of between about 400 and about 2000 Angstroms. 26. The method of claim 25, wherein the siliciding metal comprises nickel (Ni); and reacting the siliciding metal comprises performing a first thermal process at a temperature of between about 300° C. and about 450° C. to form a first state nickel silicide, removing unreacted portions of the nickel following the first thermal process, and performing a second thermal process at a temperature of between about 400° C. and about 550° C. to form a second state nickel silicide after removing the unreacted portions.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.