The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes,
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.
대표청구항▼
1. An integrated circuit chip, comprising: a silicon substrate;multiple MOS devices in and on said silicon substrate;a first metallization structure over said silicon substrate,a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a fi
1. An integrated circuit chip, comprising: a silicon substrate;multiple MOS devices in and on said silicon substrate;a first metallization structure over said silicon substrate,a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said first metallization structure; and said second contact point is at a bottom of said second opening; anda second metallization structure on said passivation layer and said first and second contact points, wherein there is no polymer layer between said second metallization structure and said passivation layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers, wherein said second metallization structure comprises a titanium-containing layer having a thickness between 0.01 and 3 micrometers, a first copper layer having a thickness between 0.05 and 3 nicrometers on said titanium-containing layer, and a second copper layer having a thickness between 2 and 100 micrometers on said first copper layer, wherein an undercut with an edge of said titanium-containing layer from an edge of said first copper layer is between 0.03 and 2 micrometers. 2. The integrated circuit chip of claim 1, wherein said second metallization structure further comprises a nickel layer on said second copper layer. 3. The integrated circuit chip of claim 1, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers. 4. The integrated circuit chip of claim 1, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper. 5. The integrated circuit chip of claim 1 further comprising a polymer layer on said second metallization structure. 6. A circuit component comprising: an integrated circuit chip comprising a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, and a second metallization structure on said passivation layer and said first and second contact points, wherein there is no polymer layer between said passivation layer and said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers and a thickness between 2 and 100 micrometers, wherein said second metallization structure comprises a titanium-containing layer having a thickness between 0.01 and 3 micrometers, a seed layer having a thickness between 0.05 and 3 micrometers on said titanium- containing layer, and a palladium layer over said seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said seed layer is between 0.03 and 2 micrometers; anda wirebond connected to said second metallization structure. 7. The circuit component of claim 6, wherein said seed layer comprises palladium. 8. The circuit component of claim 6, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers. 9. The circuit component of claim 6, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper. 10. The circuit component of claim 6, wherein said integrated circuit chip further comprises a polymer layer on said second metallization structure. 11. The circuit component of claim 6, wherein said palladium layer is electroplated. 12. A circuit component comprising: an integrated circuit chip comprising a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, and a second metallization structure on said passivation layer and said first and second contact points, wherein there is no polymer layer between said passivation layer and said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers and a thickness between 2 and 100 micrometers, wherein said second metallization structure comprises a titanium-containing layer having a thickness between 0.01 and 3 micrometers, a seed layer having a thickness between 0.05 and 3 micrometers on said titanium-containing layer, and a gold layer over said seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said seed layer is between 0.03 and 2 micrometers; anda wirebond connected to said second metallization structure. 13. The circuit component of claim 12, wherein said seed layer comprises gold. 14. The circuit component of claim 12, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers. 15. The circuit component of claim 12, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper. 16. The circuit component of claim 12, wherein said integrated circuit chip further comprises a polymer layer on said second metallization structure. 17. The circuit component of claim 12, wherein said gold layer is electroplated. 18. An integrated circuit chip, comprising: a silicon substrate;multiple MOS devices in and on said silicon substrate;a metallization structure over said silicon substrate, wherein said metallization structure comprises a damascene copper and a first adhesion layer under said damascene copper and at a sidewall of said damascene copper;a first separating layer over said metallization structure, wherein a first opening in said first separating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said first separating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said first separating layer comprises a silicon-containing compound;a first metal layer on said first separating layer and said first and second contact points, wherein there is no polymer layer between said first metal layer and said first separating layer, wherein said first contact point is connected to said second contact point through said first metal layer, wherein said first metal layer comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers, wherein said first metal layer comprises a second adhesion layer having a thickness between 0.01 and 3 micrometers, a first copper layer having a thickness between 0.05 and 3 micrometers on said second adhesion layer, and a second copper layer having a thickness between 2 and 100 micrometers on said first copper layer, wherein said second adhesion layer is at a bottom of said second copper layer, but not at a sidewall of said second copper layer, wherein an undercut with an edge of said second adhesion layer recessed from an edge of said second copper layer is between 0.03 and 2 micrometers;a second separating layer on a top surface and a sidewall of said first metal layer and on said first separating layer, wherein said second separating layer comprises a polymer; anda second metal layer on said second separating layer. 19. The integrated circuit chip of claim 18, wherein said silicon-containing compound comprises oxynitride. 20. The integrated circuit chip of claim 18 further comprising a polymer layer on said second metal layer.
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Fan, Yang-Tung; Chu, Cheng-Yu; Fan, Fu-Jier; Lin, Shih-Jane; Peng, Chiou-Shian; Chen, Yen-Ming; Lin, Kuo-Wei, Bumping process to increase bump height and to create a more robust bump structure.
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Chittipeddi Sailesh ; Cochran William T. ; Smooha Yehuda, Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein.
Fillion Raymond A. (Niskayuna NY) Wildi Eric J. (Niskayuna NY) Korman Charles S. (Schenectady NY) El-Hamamsy Sayed-Amr (Schenectady NY) Gasworth Steven M. (Glenville NY) DeVre Michael W. (Scotia NY) , Direct stacked and flip chip power semiconductor device structures.
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Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Saitoh Tatsuya (Kokubunji JPX) Yamamoto Kazumichi (Kokubunji JPX), Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections betwe.
Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX), Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof.
Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton , Integrated circuit with bonding layer over active circuitry.
Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward, Integrated circuit with bonding layer over active circuitry.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated memory cube, structure and fabrication.
Ahmad Umar M. U. (Both of Hopewell Junction NY) Kumar Ananda H. (Both of Hopewell Junction NY) Perfecto Eric D. (Wappingers Falls NY) Prasad Chandrika (Wappingers Falls NY) Purushothaman Sampath (Yor, Interconnect structure having improved metallization.
David V. Horak ; William A. Klaasen ; Thomas L. McDevitt ; Mark P. Murray ; Anthony K. Stamper, Interconnection structure and method for fabricating same.
Erdeljac John P. ; Hutter Louis Nicholas ; Khatibzadeh M. Ali ; Arch John Kenneth, Metallization outside protective overcoat for improved capacitors and inductors.
Tomasi Peter A. ; Zhao Tong ; St. Angel Lindo ; Schellinger Michael J. ; Nguyen Dien N. ; Bradley Wayne H., Method and apparatus for reducing current consumption.
Mistry Addi Burjorji ; Sarihan Vijay ; Kleffner James H. ; Carney George F., Method and apparatus for stress relief in solder bump formation on a semiconductor device.
Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
Leu, Jihperng; Wu, Chih-I; Zhou, Ying; Kloster, Grant M., Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics.
Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX), Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer.
Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect.
Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines.
Peters Johannes S. (Nijmegen NLX), Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided o.
Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
Steinhardt Paul J. (1000 Cedar Grove Rd. Wynnewood PA 19096) Taylor Philip (7801 Bustleton Ave. Philadelphia PA 19152), Methods and apparatus for eliminating Moire\interference using quasiperiodic patterns.
Cronin John Edward (Milton VT) Howell Wayne John (Williston VT) Kalter Howard Leo (Colchester VT) Marmillion Patricia Ellen (Colchester VT) Palagonia Anthony (Underhill VT) Pierson Bernadette Ann (So, Methods for precise definition of integrated circuit chip edges.
Kim, Sarah E.; Lee, Kevin J.; George, Anna M., Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow.
Laurent Basteres FR; Ahmed Mhani FR; Fran.cedilla.ois Valentin FR; Jean-Michel Karam FR, Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit.
E. Henry Stevens, Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece.
Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX), Process for forming a structure which electrically shields conductors.
Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
Quinn ; Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX, Process of forming integrated circuits with contact pads in a standard array.
Leibovitz Jacques ; Yu Park-Kee ; Zhu Ya Yun ; Cobarruviaz Maria L. ; Swindlehurst Susan J. ; Chang Cheng-Cheng ; Scholz Kenneth D., Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps.
Yong, Lois E.; Harper, Peter R.; Tran, Tu Anh; Metz, Jeffrey W.; Leal, George R.; Dinh, Dieu Van, Semiconductor device having a bond pad and method therefor.
Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori, Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film.
Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.
Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX), Semiconductor device having built-in high frequency bypass capacitor.
Ueda Tetsuya,JPX ; Tamaoka Eiji,JPX ; Aoi Nobuo,JPX, Semiconductor device having multilevel interconnection structure and method for fabricating the same.
Homma, Soichi; Miyata, Masahiro; Ezawa, Hirokazu, Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same.
Yutaka Aoki JP; Hiroshi Takenaka JP; Ichiro Mihara JP, Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise.
Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structure including a titanium barrier layer.
Schaefer William Jeffrey ; Kao Pai-Hsiang ; Kelkar Nikhil Vishwanath, Surface mount die: wafer level chip-scale package and process for making the same.
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